Line-edge roughness and the impact of stochastic processes on lithography scaling for Moore's Law

Author(s):  
Chris A. Mack
2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000986-001015
Author(s):  
Eric Huenger ◽  
Joe Lachowski ◽  
Greg Prokopowicz ◽  
Ray Thibault ◽  
Michael Gallagher ◽  
...  

As advanced packaging application space evolves and continues to deviate from the conventional shrinkage pathway predicted by Moore's law, material suppliers need to continue to work with OEMs, OSATs and Foundries to identify specific opportunities. One such opportunity continues to present itself in developing new materials to support new platforms for next generation products to support 3D chip stacking and TSV applications. The newer material sets can be established to meet more challenging design requirements associated with the demands, presented by the application from both a physical/lithographical processing and design perspective. Next generation packages requires the development of new dielectric materials that can support both the physical demands of 3D chip stacking and TSV package design aspects while maintaining strengths of the existing material platform. While vertical integration necessitates the use of thinned substrates and its associated integration challenges, there is a continuing need to support horizontal shrinkage typical of the Moore's Law, which pushes the lithography envelope requiring finer pitch and smaller feature resolution capability. This presentation identifies the strategy we have taken and highlights approach taking in the development of low temperature curable photoimageable dielectric materials with enhanced lithographic performance. We will discuss the methodology used to create benzocyclobutene based dielectric material curable at 180 °C and show how lithographic performance can be tuned to allow sub 5 micron via using broad band illumination. Finally we will review the impact of low temperature processing on the mechanical, thermal and electrical properties of this novel photoimageable dielectric material.


Author(s):  
Shankar Krishnan ◽  
Suresh V. Garimella ◽  
Greg M. Chrysler ◽  
Ravi V. Mahajan

The thermal design power trends and power densities for present and future microprocessors are investigated. The trends are derived based on Moore’s law and scaling theory. Both active and stand-by power are discussed and accounted for in the calculations. A brief discussion of various leakage power components and their impact on the power density trends is provided. Two different lower limits of heat dissipation for irreversible logic computers are discussed. These are based on the irreversibility of logic to represent one bit of information, and on the distribution of electrons to represent a bit. These limits are found to be two or more orders of magnitude lower than present-day microprocessor thermal design power trends. Further, these trends are compared to the projected trends for the desktop product sector from the International Technology Roadmap for Semiconductors (ITRS). To evaluate the thermal impact of the projected power densities, heat sink thermal resistances are calculated for a given technology target. Based on the heat sink thermal resistance trends, the evolution of an air-cooling limit consistent with Moore’s law is predicted. One viable alternative to air-cooling, i.e., the use of high-efficiency solid-state thermoelectric coolers (TECs), is explored. The impact of different parasitics on the thermoelectric figure of merit (ZT) is quantified.   This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.


2017 ◽  
Vol 50 (6) ◽  
pp. 1766-1772 ◽  
Author(s):  
Analía Fernández Herrero ◽  
Mika Pflüger ◽  
Jürgen Probst ◽  
Frank Scholze ◽  
Victor Soltwisch

Lamellar gratings are widely used diffractive optical elements; gratings etched into Si can be used as structural elements or prototypes of structural elements in integrated electronic circuits. For the control of the lithographic manufacturing process, a rapid in-line characterization of nanostructures is indispensable. Numerous studies on the determination of regular geometry parameters of lamellar gratings from optical and extreme ultraviolet (EUV) scattering highlight the impact of roughness on the optical performance as well as on the reconstruction of these structures. Thus, a set of nine lamellar Si gratings with a well defined line edge roughness or line width roughness were designed. The investigation of these structures using EUV small-angle scattering reveals a strong correlation between the type of line roughness and the angular scattering distribution. These distinct scattering patterns open new paths for the unequivocal characterization of such structures by EUV scatterometry.


2001 ◽  
Vol 705 ◽  
Author(s):  
Jonathan L. Cobb ◽  
Robert L. Brainard ◽  
Donna J. O'Connell ◽  
Paul M. Dentinger

AbstractExtreme Ultraviolet (EUV) lithography is gaining momentum as the patterning technology of choice for the semiconductor nodes with less than 70-nm half-pitch. As such, it must be ready for manufacturing in the 2006-2007 time frame, and it must be extendable to the lower limits of CMOS technology. Successful patterning of 40-nm dense lines in viable EUV photoresists indicates that today's resist materials may have the necessary resolution, but better optics are needed to verify this more rigorously. Although little is understood about the impact of line-edge roughness (LER) on device performance, it is generally assumed that EUV LER must be less than 3 nm 3σ. EUV lines have been printed with LER as low as 4 nm 3σ, but they were printed with unacceptable photospeed. Deliberate attempts to increase the photospeed while maintaining low LER have produced a resist with sizing dose of 1.7 mJ/cm2 and LER of 6.6 nm 3σ. Photospeed is important because EUV photons are difficult to create, and the photoresist must use them efficiently for economically acceptable throughput. Throughput models indicate that patterning doses may need to be 1-2 mJ/cm2, and only 30-40% of these photons will be absorbed, so the resists must be able to accommodate statistical dose fluctuations that are an appreciable fraction of the mean dose. Highly sensitive resists such as these have been produced with good LER. Since all resist materials absorb EUV radiation strongly, the photoresist layer will have to be less than 150 nm thick. Resists this thin pose problems for device manufacturing, largely because they will not have acceptable etch resistance, and this etch resistance will have to be recovered in some other way. Efforts have begun to integrate hard masks with thin resists in real device fabrication. Defect data indicate that defect densities do not increase in resist films less than 100 nm thick, and transistors, via chains, and microprocessors have all been fabricated with these thin-resist/hard-mask integrations.


Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 455
Author(s):  
Jinwoong Lee ◽  
Taeeon Park ◽  
Hongjoon Ahn ◽  
Jihwan Kwak ◽  
Taesup Moon ◽  
...  

As the physical size of MOSFET has been aggressively scaled-down, the impact of process-induced random variation (RV) should be considered as one of the device design considerations of MOSFET. In this work, an artificial neural network (ANN) model is developed to investigate the effect of line-edge roughness (LER)-induced random variation on the input/output transfer characteristics (e.g., off-state leakage current (Ioff), subthreshold slope (SS), saturation drain current (Id,sat), linear drain current (Id,lin), saturation threshold voltage (Vth,sat), and linear threshold voltage (Vth,lin)) of 5 nm FinFET. Hence, the prediction model was divided into two phases, i.e., “Predict Vth” and “Model Vth”. In the former, LER profiles were only used as training input features, and two threshold voltages (i.e., Vth,sat and Vth,lin) were target variables. In the latter, however, LER profiles and the two threshold voltages were used as training input features. The final prediction was then made by feeding the output of the first model to the input of the second model. The developed models were quantitatively evaluated by the Earth Mover Distance (EMD) between the target variables from the TCAD simulation tool and the predicted variables of the ANN model, and we confirm both the prediction accuracy and time-efficiency of our model.


Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1899
Author(s):  
Yejoo Choi ◽  
Jinwoong Lee ◽  
Jaehyuk Lim ◽  
Seungjun Moon ◽  
Changhwan Shin

In this study, the impact of the negative capacitance (NC) effect on process-induced variations, such as work function variation (WFV), random dopant fluctuation (RDF), and line edge roughness (LER), was investigated and compared to those of the baseline junctionless nanowire FET (JL-NWFET) in both linear (Vds = 0.05 V) and saturation (Vds = 0.5 V) modes. Sentaurus TCAD and MATLAB were used for the simulation of the baseline JL-NWFET and negative capacitance JL-NWFET (NC-JL-NWFET). Owing to the NC effect, the NC-JL-NWFET showed less variation in terms of device performance, such as σ[Vt], σ[SS], σ[Ion/Ioff], σ[Vt]/µ[Vt], σ[SS]/µ[SS], and σ[Ion/Ioff]/µ[Ion/Ioff], and enhanced device performance, which implies that the NC effect can successfully control the variation-induced degradation.


2005 ◽  
Vol 18 (4) ◽  
pp. 467-469 ◽  
Author(s):  
F. C. Zumsteg ◽  
K. W. Leffew ◽  
A. E. Feiring ◽  
M. K. Crawsfored ◽  
W. B. Fahnham ◽  
...  

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