scholarly journals FEASIBILITY STUDY OF 8-BIT MICROCONTROLLER APPLICATIONS FOR ETHERNET / AŠTUONIŲ SKILČIŲ MIKROVALDIKLIŲ PANAUDOJIMO GALIMYBIŲ TYRIMAS ETHERNET TINKLO ĮRENGINIUOSE

2011 ◽  
Vol 3 (1) ◽  
pp. 82-86 ◽  
Author(s):  
Lech Gulbinovič
Keyword(s):  
Feasibility Study ◽  
Processing Speed ◽  
Packet Processing ◽  
Packet Size ◽  
Code Size ◽  
Program Code ◽  
Code Compression ◽  
Speed Optimization ◽  
Packet Latency ◽  
Ethernet Controller

Feasibility study of 8-bit microcontroller applications for Ethernet is presented. Designed device is based on ATmega32 microcontroller and 10 Mbps Ethernet controller ENC28J60. Device is simulated as mass queuing theoretical model with ticket booking counter. Practical explorations are accomplished and characteristics are determined. Practical results are compared to theoretical ones. Program code and device packet processing speed optimization are discussed. Microcontroller packet processing speed and packet latency depend on packet size. For ICMP protocol packet processing speed varies 1.4–2.1 Mbps, latency – 0.8–8.4 ms. UDP protocol packet processing speed varies 1.3–1.8 Mbps, latency – 1.1–9.6 ms. Packet processing speed depends on compilation settings and program code compression level. Best results are reached on optimization le­vel ‑O3, then speed increased ~3% but program code size increased 68% comparing to –Os optimization level.

scholarly journals Applying 2-way Superscalar Technique to a 32-bit RISC Microprocessor

2013 ◽  
Vol 16 (4) ◽  
pp. 33-42
Author(s):  
Quynh Ngoc Do ◽  
Hoang Nguyen Thanh Hau
Keyword(s):  
Single Machine ◽  
Processing Speed ◽  
Program Code ◽  
Machine Cycle ◽  
Maximum Ideal ◽  
Order Execution ◽  
Instructions Per Cycle

In one-way microprocessor, the program code is executed at the maximum (ideal) rate of one instruction per cycle. In practice, due to the occurrence of branch instruction, this rate is less than 1. Superscalar architecture, when applied to a 32-bit RISC microprocessor, enables the handling of two instructions in a single machine cycle. To further increase the processing speed, the out-of-order execution is also applied to process an instruction that its operands are ready. As a result, the microprocessor which can complete two instructions per cycle is obtained.

scholarly journals Distance transform and template matching based methods for localization of barcodes and QR codes

2020 ◽  
Vol 17 (1) ◽  
pp. 161-179
Author(s):  
Melinda Katona ◽  
Péter Bodnár ◽  
László Nyúl
Keyword(s):  
Processing Speed ◽  
Template Matching ◽  
Industrial Applications ◽  
Automatic Identification ◽  
Large Set ◽  
Qr Codes ◽  
Code Size ◽  
Distance Transformation ◽  
Embedded Web ◽  
Speed And Accuracy

Visual codes play an important role in automatic identification, which became an inseparable part of industrial processes. Thanks to the revolution of smartphones and telecommunication, it also becomes more and more popular in everyday life, containing embedded web addresses or other small informative texts. While barcode reading is straightforward in images having optimal parameters (focus, illumination, code orientation, and position), localization of code regions is still challenging in many scenarios. Every setup has its own characteristics, therefore many approaches are justifiable. Industrial applications are likely to have more fixed parameters like illumination, camera type and code size, and processing speed and accuracy are the most important requirements. In everyday use, like with smartphone cameras, a wide variety of code types, sizes, noise levels and blurring can be observed, but the processing speed is often not crucial, and the image acquisition process can be repeated in order for successful detection. In this paper, we address this problem with two novel methods for localization of 1D barcodes based on template matching and distance transformation, and a third method to detect QR codes. Our proposed approaches can simultaneously localize several different types of codes. We compare the effectiveness of the proposed methods with several approaches from the literature using public databases and a large set of synthetic images as a benchmark. The evaluation shows that the proposed methods are efficient, having 84.3% Jaccard accuracy, superior to other approaches. One of the presented approaches is an improvement on our previous work. Our template matching based method is computationally more complex, however, it can be adapted to specific code types providing high accuracy. The other method uses distance transformation, which is fast and gives rough regions of interests that can contain valid visual code candidates.

scholarly journals A Videogame-Based Digital Therapeutic to Improve Processing Speed in People with Multiple Sclerosis: A Feasibility Study

2018 ◽  
Vol 8 (1) ◽  
pp. 135-145 ◽  
Author(s):  
Riley M. Bove ◽  
Gillian Rush ◽  
Chao Zhao ◽  
William Rowles ◽  
Priya Garcha ◽  
...  
Keyword(s):  
Multiple Sclerosis ◽  
Feasibility Study ◽  
Processing Speed

scholarly journals Co-design of Compiler and Hardware Techniques to Reduce Program Code Size on a VLIW Processor

2012 ◽  
Vol 15 (2) ◽  
Author(s):  
Eric J. Stotzer ◽  
Ernst L. Leiss
Keyword(s):  
Power Efficiency ◽  
Total System ◽  
Primary Concern ◽  
Compiler Optimizations ◽  
Code Size ◽  
Embedded Computing ◽  
Program Code ◽  
System Cost ◽  
Vliw Processors ◽  
Vliw Processor

Code size is a primary concern in the embedded computing community. Minimizing physical memory requirements reduces total system cost and improves performance and power efficiency. VLIW processors rely on the compiler to statically encode the ILP in the program before its execution, and because of this, code size is larger relative to other processors. In this paper we describe the co-design of compiler optimizations and processor architecture features that have progressively reduced code size across three generations of a VLIW processor.

An efficient code compression for MIPS32 processor using dictionary and bit-mask based static and dynamic frequency algorithm

2016 ◽  
Vol 35 (5) ◽  
pp. 1774-1785 ◽  
Author(s):  
G. Ramani ◽  
K. Geetha
Keyword(s):  
Design Methodology ◽  
Vital Role ◽  
Experimental Result ◽  
Code Size ◽  
Compression Technique ◽  
Compression Efficiency ◽  
Content Type ◽  
Code Compression ◽  
Efficient Code ◽  
Dynamic Frequency

Purpose Memory plays a vital role in designing embedded systems. A larger memory can accommodate more and larger applications but increases cost area, as well as energy requirements. Hence, the purpose of this paper is to propose code compression techniques to solve this issue by minimizing the code size of the application program by compressing the instructions with higher static frequency. Design/methodology/approach The idea is based on the static and dynamic frequency-based algorithm combined with bit mask and dictionary-based algorithm for MIPS32 processor, in order to minimize the code size and improves compression ratio. Findings The experimental result shows that the proposed system achieves up to 67 percent compression efficiency. Originality/value The paper presents enhanced versions of the code compression technique.

scholarly journals CODE COMPRESSION FOR THE EMBEDDED ARM/THUMB PROCESSOR

2014 ◽  
pp. 7-12
Author(s):  
Xianhong Xu ◽  
Simon Jones
Keyword(s):  
Embedded Systems ◽  
Size Reduction ◽  
Software Implementation ◽  
Instruction Set ◽  
Code Size ◽  
Code Compression ◽  
Temporary Storage ◽  
Level 2 ◽  
Code Density ◽  
Software Prototype

Previous code compression research on embedded systems was based on typical RISC instruction code. THUMB from ARM Ltd is a compacted 16-bits instruction set showing a great code density than its original 32-bits ARM instruction. Our research shows that THUMB code is compressible and a further 10-15% code size reduction on THUMB code can be expected using our proposed new architecture – Code Compressed THUMB Processor. In our proposal, Level 2 cache or additional RAM space is introduced to serve as the temporary storage for decompressed program blocks. A software implementation of the architecture is proposed and we have implemented a software prototype based on ARM922T processor, which runs on the ARMulator.

A Macintosh Interface for the Cameca Camebax-Micro Electron Microprobe

1990 ◽  
Vol 48 (1) ◽  
pp. 438-439
Author(s):  
Carl E. Henderson
Keyword(s):  
Electron Microprobe ◽  
Processing Speed ◽  
Word Processing ◽  
State Of The Art ◽  
Computer Control ◽  
Third Party ◽  
Disk Storage ◽  
The Past ◽  
User Facility ◽  
Instrument Control

Over the past few years it has become apparent in our multi-user facility that the computer system and software supplied in 1985 with our CAMECA CAMEBAX-MICRO electron microprobe analyzer has the greatest potential for improvement and updating of any component of the instrument. While the standard CAMECA software running on a DEC PDP-11/23+ computer under the RSX-11M operating system can perform almost any task required of the instrument, the commands are not always intuitive and can be difficult to remember for the casual user (of which our laboratory has many). Given the widespread and growing use of other microcomputers (such as PC’s and Macintoshes) by users of the microprobe, the PDP has become the “oddball” and has also fallen behind the state-of-the-art in terms of processing speed and disk storage capabilities. Upgrade paths within products available from DEC are considered to be too expensive for the benefits received. After using a Macintosh for other tasks in the laboratory, such as instrument use and billing records, word processing, and graphics display, its unique and “friendly” user interface suggested an easier-to-use system for computer control of the electron microprobe automation. Specifically a Macintosh IIx was chosen for its capacity for third-party add-on cards used in instrument control.

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