scholarly journals A True Full-Duplex IO (TFD-IO) with Background SI cancellation for High-Density Interfaces

2021 ◽  
Author(s):  
Sandeep Goyal ◽  
Shalabh Gupta ◽  
Ganpat Anant Parulekar
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
High Density ◽  
The Self ◽  
Full Duplex ◽  
Density Interfaces

In this work, we have proposed and experimentally demonstrated a true full-duplex IO (TFD-IO) for high-speed high-density interfaces. The proposed TFD-IO can be used as an independent module that converts a unidirectional IO/interconnect to a fully bidirectional IO/interconnect, to ideally double the throughput of the high-speed interface. The TFD-IO uses a correlation-based technique to cancel the self-interference (SI) and echoes adaptively in the background. The signals transmitted from the near-end and the far-end can use independent baud nm CMOS technology, and demonstrated with bidirectional throughputs of up to 12.8 Gb/s.

scholarly journals A True Full-Duplex IO (TFD-IO) with Background SI Cancellation for High-Density Interfaces

2021 ◽  
Author(s):  
Sandeep Goyal ◽  
Ganpat Anant Parulekar ◽  
Shalabh Gupta
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
High Density ◽  
The Self ◽  
Full Duplex ◽  
Concept Design ◽  
Proof Of Concept ◽  
Density Interfaces

In this work, we have proposed and experimentally demonstrated a true full-duplex IO (TFD-IO) for high-speed high-density interfaces. The proposed TFD-IO can be used as an independent module that converts a unidirectional IO/interconnect to a fully bidirectional IO/interconnect, to ideally double the throughput of the high-speed interface. <br>The TFD-IO uses a correlation-based technique to cancel the self-interference (SI) adaptively in the background. The signals transmitted from the near-end and the far-end can use independent baud-rates and signaling schemes in a TFD-IO. A proof-of-concept design of the TFD-IO module has been fabricated in a 65 nm CMOS technology, and demonstrated with bidirectional throughputs of up to 12.8\,Gb/s.

scholarly journals A True Full-Duplex IO (TFD-IO) with Background SI cancellation for High-Density Interfaces

2021 ◽  
Author(s):  
Sandeep Goyal ◽  
Shalabh Gupta ◽  
Ganpat Anant Parulekar
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
High Density ◽  
The Self ◽  
Full Duplex ◽  
Density Interfaces

In this work, we have proposed and experimentally demonstrated a true full-duplex IO (TFD-IO) for high-speed high-density interfaces. The proposed TFD-IO can be used as an independent module that converts a unidirectional IO/interconnect to a fully bidirectional IO/interconnect, to ideally double the throughput of the high-speed interface. The TFD-IO uses a correlation-based technique to cancel the self-interference (SI) and echoes adaptively in the background. The signals transmitted from the near-end and the far-end can use independent baud nm CMOS technology, and demonstrated with bidirectional throughputs of up to 12.8 Gb/s.

scholarly journals A True Full-Duplex IO (TFD-IO) with Background SI Cancellation for High-Density Interfaces

2021 ◽  
Author(s):  
Sandeep Goyal ◽  
Ganpat Anant Parulekar ◽  
Shalabh Gupta
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
High Density ◽  
The Self ◽  
Full Duplex ◽  
Concept Design ◽  
Proof Of Concept ◽  
Density Interfaces

In this work, we have proposed and experimentally demonstrated a true full-duplex IO (TFD-IO) for high-speed high-density interfaces. The proposed TFD-IO can be used as an independent module that converts a unidirectional IO/interconnect to a fully bidirectional IO/interconnect, to ideally double the throughput of the high-speed interface. <br>The TFD-IO uses a correlation-based technique to cancel the self-interference (SI) adaptively in the background. The signals transmitted from the near-end and the far-end can use independent baud-rates and signaling schemes in a TFD-IO. A proof-of-concept design of the TFD-IO module has been fabricated in a 65 nm CMOS technology, and demonstrated with bidirectional throughputs of up to 12.8\,Gb/s.

C/sup 2/L: A new high-speed high-density bulk CMOS technology

1977 ◽  
Vol 12 (4) ◽  
pp. 344-349 ◽  
Author(s):  
A.G.F. Dingwall ◽  
R.E. Stricker
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
High Density

scholarly journals A 16 Gbps, Full-Duplex Transceiver over Lossy On-Chip Interconnects in 28 nm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 717
Author(s):  
Arash Ebrahimi Jarihani ◽  
Sahar Sarafi ◽  
Michael Koeberle ◽  
Johannes Sturm ◽  
Andrea M. Tonello
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
Supply Voltage ◽  
Impedance Matching ◽  
Low Complexity ◽  
Cmos Technology ◽  
Data Rate ◽  
Full Duplex ◽  
On Chip ◽  
28 Nm

A high-speed full-duplex transceiver (FDT) over lossy on-chip interconnects is presented. The FDT employs a hybrid circuit to separate the inbound and outbound signals from each other and also performs echo-cancellation with the help of the main and the auxiliary drivers. A hybrid MOS device is utilized for impedance matching and conversion of the received voltage signal into a current signal for amplification. Moreover, a compensation capacitance ( C c ) is used at the output of the main driver to minimize the residual echo signal and achieve a higher data rate. The entire FDT architecture has been designed in TSMC 28 nm CMOS standard process with 0.9 V supply voltage. The performance results validate a 16 Gbps FD operation with a root-mean-square (RMS) jitter of 16.4 ps, and a power efficiency of 0.16 pJ/b/mm over a 5 mm on-chip interconnect without significant effect due to process-voltage-temperature (PVT) variations. To the best knowledge of the authors, this work shows the highest achievable full-duplex data rate, among the solutions reported in the literature to date, yet with low complexity, low layout area of 1581 μ m 2 and competitive power efficiency.

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