Space systems. Semiconductor integrated circuits for space applications. Design requirements

2016 ◽  
Keyword(s):  
Integrated Circuits ◽  
Space Systems ◽  
Space Applications ◽  
Design Requirements

scholarly journals Self-healing materials for space applications: overview of present development and major limitations

2021 ◽  
Author(s):  
Laura Pernigoni ◽  
Ugo Lafont ◽  
Antonio Mattia Grande
Keyword(s):  
Orbital Debris ◽  
Space Environment ◽  
Technological Evolution ◽  
Self Healing ◽  
Space Systems ◽  
Space Applications ◽  
Structural Fatigue ◽  
Operational Life ◽  
Technological Limitations ◽  
Human Exploration

AbstractIn the last decade, self-healing materials have become extremely appealing for the field of space applications, due to their technological evolution and the consequent possibility of designing space systems and structures able to repair autonomously after damage arising from impacts with micrometeoroids and orbital debris, from accidental contact with sharp objects, from structural fatigue or simply due to material aging. The integration of these novel materials in the design of spacecraft structures would result in increased reliability and safety leading to longer operational life and missions. Such concepts will bring a decisive boost enabling new mission scenario for the establishment of new orbital stations, settlement on the Moon and human exploration of Mars.The proposed review aims at presenting the newest and most promising self-healing materials and associated technologies for space application, along with the issues related to their current technological limitations in combination with the effect of the space environment. An introductory part about the outlooks and challenges of space exploration and the self-healing concept is followed by a brief description of the space environment and its possible effects on the performance of materials. Self-healing materials are then analysed in detail, moving from the general intrinsic and extrinsic categories down to the specific mechanisms.

Parametric Analysis of a Thermally Actuated Cooling System for Space Applications

2000 ◽  
Author(s):  
K. Freudenberg ◽  
W. E. Lear ◽  
S. A. Sherif
Keyword(s):  
Thermal Management ◽  
Parametric Analysis ◽  
Cooling System ◽  
Space Applications ◽  
Development Stages ◽  
Prototype Development ◽  
Design Cycle ◽  
Subsystem Design ◽  
Design Requirements ◽  
Thermally Actuated

Abstract Integration of new and existing technologies for thermal management will be required to meet the challenges associated with the increased need for an efficient, lightweight, heat rejection system. Subsystem design requirements, such as thermal and mass management, must be brought into me design cycle to establish an optimal configuration. This paper provides a parametric analysis that determines a range of parameters under which a proposed system becomes viable from a weight management standpoint. The analysis can be applied to essentially any space-operated thermally-actuated heat pump with power and refrigeration subsystems. By applying the techniques demonstrated in this paper, designers can identify and optimize conceptual configurations during the initial prototype development stages to reduce payload weight and increase financial savings.

scholarly journals A High Performance Global Routing Algorithm on Julia Parallel Computing Platform

2021 ◽  
Vol 9 ◽  
pp. 103-108
Author(s):  
Meenakshi Agarwalla ◽  
Manash Pratim Sarma ◽  
Kandarpa Kumar Sarma
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Routing Algorithm ◽  
Global Routing ◽  
Careful Attention ◽  
Additional Advantage ◽  
C Language ◽  
Computing Platform ◽  
Sequential Processing ◽  
Design Requirements

o keep pace with the design requirements of Integrated Circuits (ICs), parallel processing is adopted. The path to be routed between two nodes may or may not be dependent on the previously routed paths. The solution requires careful attention in distributing the nets to be routed to different processors. Previous work on allocating the tasks to processors has been quite successful, reporting upto 3x improvement on 4 cores and 5x improvement on 8 core machine. The advantage of increasing the number of cores diminishes with each added processor and the challenge lies in being able to maintain the improvement per added core. The existing techniques of distributing the nets cannot provide additional advantage of using more than 8 cores. This paper improves the work on parallelizing global routing using a technique of balancing the load on the processors for better utilization of the resources. A relatively new budding platform Julia has been used which provides the ease of programming while maintaining the performance of the C language. Technique used in this paper has enabled to use 16 cores with routing solutions obtained in 0.8 minutes achieving 12.5 times speedup compared to sequential processing on a single core

scholarly journals High-Density Interconnect Technology Assessment of Printed Circuit Boards for Space Applications

2020 ◽  
Vol 17 (3) ◽  
pp. 79-88
Author(s):  
Maarten Cauwe ◽  
Bart Vandevelde ◽  
Chinmay Nawghane ◽  
Marnix Van De Slyeke ◽  
Erwin Bosman ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Printed Circuit Boards ◽  
Digital Signal ◽  
High Density ◽  
Circuit Boards ◽  
Space Applications ◽  
Track Width ◽  
Printed Circuit ◽  
Field Programmable ◽  
Space Projects

Abstract High-density interconnect (HDI) printed circuit boards (PCBs) and associated assemblies are essential to allow space projects to benefit from the ever increasing complexity and functionality of modern integrated circuits such as field-programmable gate arrays, digital signal processors and application processors. Increasing demands for functionality translate into higher signal speeds combined with an increasing number of input/outputs (I/Os). To limit the overall package size, the contact pad pitch of the components is reduced. The combination of a high number of I/Os with a reduced pitch places additional demands onto the PCB, requiring the use of laser-drilled microvias, high-aspect ratio core vias, and small track width and spacing. Although the associated advanced manufacturing processes have been widely used in commercial, automotive, medical, and military applications, reconciling these advancements in capability with the reliability requirements for space remains a challenge. Two categories of the HDI technology are considered: two levels of staggered microvias (basic HDI) and (up to) three levels of stacked microvias (complex HDI). In this article, the qualification of the basic HDI technology in accordance with ECSS-Q-ST-70-60C is described. At 1.0-mm pitch, the technology passes all testing successfully. At .8-mm pitch, failures are encountered during interconnection stress testing and conductive anodic filament testing. These failures provide the basis for updating the design rules for HDI PCBs.

scholarly journals Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs

Eng ◽  
2021 ◽  
Vol 2 (4) ◽  
pp. 620-631
Author(s):  
Peng Lu ◽  
Can Yang ◽  
Yifei Li ◽  
Bo Li ◽  
Zhengsheng Han
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Gate Dielectric ◽  
Capture Rate ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Threshold Voltage Shift ◽  
Space Applications ◽  
Effect Transistor ◽  
Aided Design

The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined with a gate dielectric de-footing technique, which has been readily developed for the 14 nm node FinFETs, is proposed as an effective method for SOI FinFETs’ TID hardening. More importantly, the governing mechanism is thoroughly investigated using fully calibrated technology computer-aided design (TCAD) simulations to guide design optimizations. The analysis demonstrates that the 3D rad-hard design can modulate the leakage path in 14 nm node n-type SOI FinFETs, effectively suppress the transistors’ sensitivity to the TID charge and reduce the threshold voltage shift by >2×. Furthermore, the rad-hard design can reduce the electric field in the BOX region and lower its charge capture rate under radiation, further improving the transistor’s robustness.

scholarly journals Investigation of Heavy-Ion Induced Single-Event Transient in 28 nm Bulk Inverter Chain

Symmetry ◽  
2020 ◽  
Vol 12 (4) ◽  
pp. 624
Author(s):  
Anquan Wu ◽  
Bin Liang ◽  
Yaqing Chi ◽  
Zhenyu Wu
Keyword(s):  
Integrated Circuits ◽  
Heavy Ions ◽  
Heavy Ion ◽  
High Energy ◽  
Advanced Technology ◽  
Sensitive Volume ◽  
Single Event ◽  
Space Applications ◽  
Order Of Magnitude ◽  
28 Nm

The reliability of integrated circuits under advanced process nodes is facing more severe challenges. Single-event transients (SET) are an important cause of soft errors in space applications. The SET caused by heavy ions in the 28 nm bulk silicon inverter chains was studied. A test chip with good symmetry layout design was fabricated based on the 28 nm process, and the chip was struck by using 5 kinds of heavy ions with different linear energy transfer (LET) values on heavy-ion accelerator. The research results show that in advanced technology, smaller sensitive volume makes SET cross-section measured at 28 nm smaller than 65 nm by an order of magnitude, the lower critical charge required to generate SET will increase the reliability threat of low-energy ions to the circuit, and high-energy ions are more likely to cause single-event multiple transient (SEMT), which cannot be ignored in practical circuits. The transients pulse width data can be used as a reference for SET modeling in complex circuits.

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