The Use of Advanced Silicon CMOS Transistor as Hardness-By-Design Technique to Improve Radiation Tolerance for Integrated Circuits Dedicated to Space Applications

2014 ◽  
Author(s):  
Leonardo Navarenho de Souza Fino ◽  
Rafael Navarenho de Souza
Keyword(s):  
Integrated Circuits ◽  
Radiation Tolerance ◽  
Design Technique ◽  
Space Applications ◽  
Cmos Transistor ◽  
Silicon Cmos

scholarly journals Radiation tolerance of two-dimensional material-based devices for space applications

2019 ◽  
Vol 10 (1) ◽  
Author(s):  
Tobias Vogl ◽  
Kabilan Sripathy ◽  
Ankur Sharma ◽  
Prithvi Reddy ◽  
James Sullivan ◽  
...  
Keyword(s):  
Radiation Tolerance ◽  
Two Dimensional ◽  
Space Applications

scholarly journals Key Technologies for THz Wireless Link by Silicon CMOS Integrated Circuits

Photonics ◽  
2018 ◽  
Vol 5 (4) ◽  
pp. 50 ◽  
Author(s):  
Minoru Fujishima
Keyword(s):  
Integrated Circuits ◽  
Silicon Germanium ◽  
Cmos Integrated Circuits ◽  
Future Research ◽  
Wireless Transceivers ◽  
Terahertz Band ◽  
Silicon Integrated Circuits ◽  
Terahertz Communication ◽  
Bicmos Integrated Circuits ◽  
Silicon Cmos

In terahertz-band communication using ultra-high frequencies, compound semiconductors with superior high-frequency performance have been used for research to date. Terahertz communication using the 300 GHz band has nonetheless attracted attention based on the expectation that an unallocated frequency band exceeding 275 GHz can be used for communication in the future. Research into wireless transceivers using BiCMOS integrated circuits with silicon germanium transistors and advanced miniaturized CMOS integrated circuits has increased in this 300 GHz band. In this paper, we will outline the terahertz communication technology using silicon integrated circuits available from mass production, and discuss its applications and future.

scholarly journals High-Density Interconnect Technology Assessment of Printed Circuit Boards for Space Applications

2020 ◽  
Vol 17 (3) ◽  
pp. 79-88
Author(s):  
Maarten Cauwe ◽  
Bart Vandevelde ◽  
Chinmay Nawghane ◽  
Marnix Van De Slyeke ◽  
Erwin Bosman ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Printed Circuit Boards ◽  
Digital Signal ◽  
High Density ◽  
Circuit Boards ◽  
Space Applications ◽  
Track Width ◽  
Printed Circuit ◽  
Field Programmable ◽  
Space Projects

Abstract High-density interconnect (HDI) printed circuit boards (PCBs) and associated assemblies are essential to allow space projects to benefit from the ever increasing complexity and functionality of modern integrated circuits such as field-programmable gate arrays, digital signal processors and application processors. Increasing demands for functionality translate into higher signal speeds combined with an increasing number of input/outputs (I/Os). To limit the overall package size, the contact pad pitch of the components is reduced. The combination of a high number of I/Os with a reduced pitch places additional demands onto the PCB, requiring the use of laser-drilled microvias, high-aspect ratio core vias, and small track width and spacing. Although the associated advanced manufacturing processes have been widely used in commercial, automotive, medical, and military applications, reconciling these advancements in capability with the reliability requirements for space remains a challenge. Two categories of the HDI technology are considered: two levels of staggered microvias (basic HDI) and (up to) three levels of stacked microvias (complex HDI). In this article, the qualification of the basic HDI technology in accordance with ECSS-Q-ST-70-60C is described. At 1.0-mm pitch, the technology passes all testing successfully. At .8-mm pitch, failures are encountered during interconnection stress testing and conductive anodic filament testing. These failures provide the basis for updating the design rules for HDI PCBs.

scholarly journals Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs

Eng ◽  
2021 ◽  
Vol 2 (4) ◽  
pp. 620-631
Author(s):  
Peng Lu ◽  
Can Yang ◽  
Yifei Li ◽  
Bo Li ◽  
Zhengsheng Han
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Gate Dielectric ◽  
Capture Rate ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Threshold Voltage Shift ◽  
Space Applications ◽  
Effect Transistor ◽  
Aided Design

The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined with a gate dielectric de-footing technique, which has been readily developed for the 14 nm node FinFETs, is proposed as an effective method for SOI FinFETs’ TID hardening. More importantly, the governing mechanism is thoroughly investigated using fully calibrated technology computer-aided design (TCAD) simulations to guide design optimizations. The analysis demonstrates that the 3D rad-hard design can modulate the leakage path in 14 nm node n-type SOI FinFETs, effectively suppress the transistors’ sensitivity to the TID charge and reduce the threshold voltage shift by >2×. Furthermore, the rad-hard design can reduce the electric field in the BOX region and lower its charge capture rate under radiation, further improving the transistor’s robustness.

Silicon CMOS-transistor-based detection up to 4.25 THz

2011 ◽  
Author(s):  
S. Boppel ◽  
A. Lisauskas ◽  
D. Seliuta ◽  
L. Minkevicius ◽  
I. Kasalynas ◽  
...  
Keyword(s):  
Cmos Transistor ◽  
Silicon Cmos
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