Description of a parametrized European mini test chip

2015 ◽  
Keyword(s):  
Test Chip

scholarly journals CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 443
Author(s):  
Mihaela-Daniela Dobre ◽  
Philippe Coll ◽  
Gheorghe Brezeanu
Keyword(s):  
Electrostatic Discharge ◽  
New Technology ◽  
Test Chip ◽  
Technology Node ◽  
Ground Resistance ◽  
Maximum Resistance ◽  
Device Model ◽  
Protection Method ◽  
Esd Protection ◽  
Protection Devices

This paper proposes an investigation of a CDM (charge device model) electrostatic discharge (ESD) protection method used in submicronic input–output (I/O) structures. The modeling of the commonly used ESD protection devices as well as the modeling of the breakdown caused by ESD is not accurate using traditional commercial tools, hence the need for test-chip implementation, whenever a new technology node is used in production. The proposed method involves defining, implementing, testing, and concluding on one test-chip structure named generically “CDM ground resistance”. The structure assesses the maximum ground resistance allowed for the considered technology for which CDM protection is assured. The findings are important because they will be actively used as CDM protection for all I/O structures developed in the considered submicronic technology node. The paper will conclude on the constraints in terms of maximum resistance of ground metal track allowed to be CDM protected.

Demonstration of Yield Improvement for On-Via MTJ Using a 2-Mbit 1T-1MTJ STT-MRAM Test Chip

2016 ◽  
Author(s):  
Hiroki Koike ◽  
Sadahiko Miura ◽  
Hiroaki Honjo ◽  
Toshinari Watanabe ◽  
Hideo Sato ◽  
...  
Keyword(s):  
Test Chip ◽  
Yield Improvement

Back-end soft and hard defect monitoring using a single test chip

2011 ◽  
Vol 51 (6) ◽  
pp. 1136-1141
Author(s):  
Fabrice Rigaud ◽  
Jean-Michel Portal ◽  
Hassen Aziza ◽  
Didier Nee ◽  
Julien Vast ◽  
...  
Keyword(s):  
Single Test ◽  
Test Chip
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