scholarly journals An Ultrafast Active Quenching Active Reset Circuit with 50% SPAD Afterpulsing Reduction in a 28 nm FD-SOI CMOS Technology Using Body Biasing Technique

Sensors ◽  
2021 ◽  
Vol 21 (12) ◽  
pp. 4014
Author(s):  
Mohammadreza Dolatpoor Lakeh ◽  
Jean-Baptiste Kammerer ◽  
Enagnon Aguénounon ◽  
Dylan Issartel ◽  
Jean-Baptiste Schell ◽  
...  
Keyword(s):  
Single Photon ◽  
Cmos Technology ◽  
The Body ◽  
Silicon On Insulator ◽  
Experimental Results ◽  
Fully Depleted ◽  
Body Biasing ◽  
Fast Quenching ◽  
28 Nm ◽  
Soi Cmos

An ultrafast Active Quenching—Active Reset (AQAR) circuit is presented for the afterpulsing reduction in a Single Photon Avalanche Diode (SPAD). The proposed circuit is designed in a 28 nm Fully Depleted Silicon On Insulator (FD-SOI) CMOS technology. By exploiting the body biasing technique, the avalanche is detected very quickly and, consequently, is quenched very fast. The fast quenching decreases the avalanche charges, therefore resulting in the afterpulsing reduction. Both post-layout and experimental results are presented and are highly in accordance with each other. It is shown that the proposed AQAR circuit is able to detect the avalanche in less than 40 ps and reduce the avalanche charge and the afterpulsing up to 50%.

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

scholarly journals High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS

2020 ◽  
Vol 10 (3) ◽  
pp. 27
Author(s):  
Andrea Ballo ◽  
Alfio Dario Grasso ◽  
Salvatore Pennisi ◽  
Chiara Venezia
Keyword(s):  
Resonant Frequency ◽  
Performance Optimization ◽  
Cmos Technology ◽  
Second Order ◽  
Silicon On Insulator ◽  
Circuit Performance ◽  
Fully Depleted ◽  
Current Consumption ◽  
28 Nm ◽  
Soi Cmos

Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology offers the possibility of circuit performance optimization with reduction of both topology complexity and power consumption. These advantages are fully exploited in this paper in order to develop a new topology of active continuous-time second-order bandpass filter with maximum resonant frequency in the range of 1 GHz and wide electrically tunable quality factor requiring a very limited quiescent current consumption below 10 μA. Preliminary simulations that were carried out using the 28-nm FD-SOI technology from STMicroelectronics show that the designed example can operate up to 1.3 GHz of resonant frequency with tunable Q ranging from 90 to 370, while only requiring 6 μA standby current under 1-V supply.

scholarly journals Evidence of Limitations of the Transconductance-to-Drain-Current Method (gm/Id) for Transistor Sizing in 28 nm UTBB FD-SOI Transistors

2020 ◽  
Vol 10 (2) ◽  
pp. 17
Author(s):  
Leonardo Barboni
Keyword(s):  
Low Voltage ◽  
Current Method ◽  
Drain Current ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Thin Body ◽  
Fully Depleted ◽  
Circuit Simulator ◽  
Transistor Sizing ◽  
28 Nm

The transconductance-to-drain-current method is a transistor sizing methodology that is commonly used in CMOS technology. In this study, we explored by means of simulations, a case of study and three figures of merit used for the method, and we conclude for the first time that the method should be reformulated. The study has been performed on Ultra-Thin Body and Buried Fully Depleted Silicon-On-Insulator 28 nm low-voltage-threshold NFET commercial technology (UTBB FD-SOI), and the simulations were performed via Spectre Circuit Simulator, by using the device model-card. To our knowledge, no previous attempts have been made to assess the method capability, and we collected very important results that infer that the method should be reformulated or considered incomplete for use with this technology, which has an impact and ramifications on the field of process modeling, simulation and circuit design.

RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology

2003 ◽  
Vol 24 (4) ◽  
pp. 251-253 ◽  
Author(s):  
Sang Lam ◽  
Hui Wan ◽  
Pin Su ◽  
P.W. Wyatt ◽  
C.L. Chen ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Fully Depleted ◽  
Gate Structure ◽  
Soi Cmos
Sign in / Sign up

Export Citation Format

Share Document