RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology

2003 ◽  
Vol 24 (4) ◽  
pp. 251-253 ◽  
Author(s):  
Sang Lam ◽  
Hui Wan ◽  
Pin Su ◽  
P.W. Wyatt ◽  
C.L. Chen ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Fully Depleted ◽  
Gate Structure ◽  
Soi Cmos

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

Fully depleted SOI-CMOS technology for high temperature IC applications

1997 ◽  
Vol 46 (1-3) ◽  
pp. 1-7 ◽  
Author(s):  
B. Gentinne ◽  
J.-P. Eggermont ◽  
D. Flandre ◽  
J.-P. Colinge
Keyword(s):  
High Temperature ◽  
Cmos Technology ◽  
Fully Depleted ◽  
Soi Cmos

scholarly journals Design and Characterization of Backside Termination Structures for Thick Fully-Depleted MAPS

Sensors ◽  
2021 ◽  
Vol 21 (11) ◽  
pp. 3809
Author(s):  
Thomas Corradino ◽  
Gian-Franco Dalla Betta ◽  
Lorenzo De Cilladi ◽  
Coralie Neubüser ◽  
Lucio Pancheri
Keyword(s):  
Breakdown Voltage ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
High Resistivity ◽  
Worst Case ◽  
Fully Depleted ◽  
Active Pixel ◽  
Pixel Sensors ◽  
Full Depletion

Fully Depleted Monolithic Active Pixel Sensors (FD-MAPS) represent an appealing alternative to hybrid detectors for radiation imaging applications. We have recently demonstrated the feasibility of FD-MAPS based on a commercial 110 nm CMOS technology, adapted using high-resistivity substrates and backside post-processing. A p/n junction diode, fabricated on the detector backside using low-temperature processing steps after the completion of the front-side Back End of Line (BEOL), is reverse-biased to achieve the full depletion of the substrate and thus fast charge collection by drift. Test diodes including termination structures with different numbers of floating guard rings and different pitches were fabricated together with other Process Control Monitor structures. In this paper, we present the design of the backside diodes, together with results from the electrical characterization of the test devices, aiming to improve understanding of the strengths and limitations of the proposed approach. Characterization results obtained on several wafers demonstrate the effectiveness of the termination rings in increasing the breakdown voltage of the backside diodes and in coping with the variability of the passivation layer characteristics. A breakdown voltage exceeding 400 V in the worst case was demonstrated in devices with 30 guard rings with 6 μm pitch, thus enabling the full depletion of high-resistivity substrates with a thickness larger than or equal to 300 μm. Additionally, we show the first direct comparison for this technology of measured pixel characteristics with 3D TCAD simulations, proving a good agreement in the extracted operating voltages.

Sign in / Sign up

Export Citation Format

Share Document