scholarly journals A Highly Reliable, 5.8 GHz DSRC Wake-Up Receiver with an Intelligent Digital Controller for an ETC System

Sensors ◽  
2020 ◽  
Vol 20 (14) ◽  
pp. 4012 ◽  
Author(s):  
Imran Ali ◽  
Muhammad Asif ◽  
Muhammad Riaz Ur Rehman ◽  
Danial Khan ◽  
Huo Yingge ◽  
...  
Keyword(s):  
High Reliability ◽  
Digital Controller ◽  
Signal Frequency ◽  
Frequency Variation ◽  
Cmos Process ◽  
Rf Transceiver ◽  
Chip Area ◽  
Current Consumption ◽  
Toll Collection ◽  
Complex Analog

In this article, a highly reliable radio frequency (RF) wake-up receiver (WuRx) is presented for electronic toll collection (ETC) applications. An intelligent digital controller (IDC) is proposed as the final stage for improving WuRx reliability and replacing complex analog blocks. With IDC, high reliability and accuracy are achieved by sensing and ensuring the successive, configurable number of wake-up signal cycles before enabling power-hungry RF transceiver. The IDC and range communication (RC) oscillator current consumption is reduced by a presented self-hibernation technique during the non-wake-up period. For accommodating wake-up signal frequency variation and enhancing WuRx accuracy, a digital hysteresis is incorporated. To avoid uncertain conditions during poor and false wake-up, a watch-dog timer for IDC self-recovery is integrated. During wake-up, the digital controller consumes 34.62 nW power and draws 38.47 nA current from a 0.9 V supply. In self-hibernation mode, its current reduces to 9.7 nA. It is fully synthesizable and needs 809 gates for its implementation in a 130 nm CMOS process with a 94 × 82 µm2 area. The WuRx measured power consumption is 2.48 µW, has −46 dBm sensitivity, and a 0.484 mm² chip area.

scholarly journals RF Transceiver for the Multi-Mode Radar Applications

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1563
Author(s):  
Jae Kwon Ha ◽  
Chang Kyun Noh ◽  
Jin Seop Lee ◽  
Ho Jin Kang ◽  
Yu Min Kim ◽  
...  
Keyword(s):  
Long Range ◽  
Integrated Circuit ◽  
Flicker Noise ◽  
Noise Figure ◽  
Supply Voltage ◽  
Doppler Frequency ◽  
Cmos Process ◽  
Rf Transceiver ◽  
Dc Offset ◽  
Multi Mode

In this work, a multi-mode radar transceiver supporting pulse, FMCW and CW modes was designed as an integrated circuit. The radars mainly detect the targets move by using the Doppler frequency which is significantly affected by flicker noise of the receiver from several Hz to several kHz. Due to this flicker noise, the long-range detection performance of the radars is greatly reduced, and the accuracy of range to the target and velocity is also deteriorated. Therefore, we propose a transmitter that suppresses LO leakage in consideration of long-range detection, target distance, velocity, and noise figure. We also propose a receiver structure that suppresses DC offset due to image signal and LO leakage. The design was conducted with TSMC 65 nm CMOS process, and the designed and fabricated circuit consumes a current of 265 mA at 1.2 V supply voltage. The proposed transmitter confirms the LO leakage suppression of 37 dB at 24 GHz. The proposed receiver improves the noise figure by about 20 dB at 100 Hz by applying a double conversion architecture and an image rejection, and it illustrates a DC rejection of 30 dB. Afterwards, the operation of the pulse, FMCW, and CW modes of the designed radar in integrated circuit was confirmed through experiment using a test PCB.

A ±3.07% frequency variation clock generator implemented using HV CMOS process

2015 ◽  
Vol 46 (4) ◽  
pp. 285-290 ◽  
Author(s):  
Chua-Chin Wang ◽  
Deng-Shian Wang ◽  
Tzu-Chiao Sung ◽  
Yi-Jie Hsieh ◽  
Tzung-Je Lee
Keyword(s):  
Frequency Variation ◽  
Cmos Process ◽  
Clock Generator

Ground-Adjustable Inductor for Wide-Tuning VCO Design

2012 ◽  
Vol 256-259 ◽  
pp. 2373-2378
Author(s):  
Wu Shiung Feng ◽  
Chin I Yeh ◽  
Ho Hsin Li ◽  
Cheng Ming Tsao
Keyword(s):  
Power Consumption ◽  
Tuning Range ◽  
Supply Voltage ◽  
Wide Band ◽  
Ultra Wide Band ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Wide Tuning Range ◽  
Chip Area ◽  
Ground Plate

A wide-tuning range voltage-controlled oscillator (VCO) with adjustable ground-plate inductor for ultra-wide band (UWB) application is presented in this paper. The VCO was implemented by standard 90nm CMOS process at 1.2V supply voltage and power consumption of 6mW. The tuning range from 13.3 GHz to 15.6 GHz with phase noise between -99.98 and -115dBc/Hz@1MHz is obtained. The output power is around -8.7 to -9.6dBm and chip area of 0.77x0.62mm2.

A CMOS Temperature Sensor with a Maximum Accuracy of 1.6 °C after One-Point Calibration

2013 ◽  
Vol 336-338 ◽  
pp. 216-220
Author(s):  
Chun Chi Chen ◽  
Keng Chih Liu ◽  
Shih Hao Lin
Keyword(s):  
Temperature Sensor ◽  
Pulse Generator ◽  
Circuit Complexity ◽  
Absolute Temperature ◽  
Cmos Process ◽  
Chip Area ◽  
Test Cost Reduction ◽  
Linear Delay ◽  
Time Amplifier ◽  
Fine Resolution

This paper presents a time-domain CMOS oscillator-based temperature sensor with one-point calibration for test cost reduction. Compared with the former CMOS sensors with linear delay lines, the proposed work composed of a temperature-to-pulse generator with adjustable time gain and a time-to-digital converter (TDC) can achieve lower circuit complexity and smaller area. A temperature-dependent oscillator for temperature sensing was used to generate the period width proportional to absolute temperature (PTAT). With the help of calibration circuit, an adjustable-gain time amplifier was adopted to dynamically adjust the amplified width that was converted by the TDC into the corresponding digital code. After calibration, the fluctuation of the sensor output with process variation can be greatly reduced. The maximum inaccuracy after one-point calibration for six package chips was 1.6 °C within a 0 80 °C temperature range. The proposed sensor fabricated in a 0.35-μm CMOS process occupied a chip area of merely 0.07 mm2, achieved a fine resolution of 0.047 °C/LSB, and consumed a low power of 25 μW@10 samples/s.

scholarly journals Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process

Sensors ◽  
2022 ◽  
Vol 22 (2) ◽  
pp. 504
Author(s):  
Ranran Zhao ◽  
Yuming Zhang ◽  
Hongliang Lv ◽  
Yue Wu
Keyword(s):  
Maximum Output Power ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Signal Frequency ◽  
Maximum Output ◽  
Voltage Controlled Oscillator ◽  
Chip Area ◽  
Frequency Source ◽  
A Charge

This paper realized a charge pump phase locked loop (CPPLL) frequency source circuit based on 0.15 μm Win GaAs pHEMT process. In this paper, an improved fully differential edge-triggered frequency discriminator (PFD) and an improved differential structure charge pump (CP) are proposed respectively. In addition, a low noise voltage-controlled oscillator (VCO) and a static 64:1 frequency divider is realized. Finally, the phase locked loop (PLL) is realized by cascading each module. Measurement results show that the output signal frequency of the proposed CPPLL is 3.584 GHz–4.021 GHz, the phase noise at the frequency offset of 1 MHz is −117.82 dBc/Hz, and the maximum output power is 4.34 dBm. The chip area is 2701 μm × 3381 μm, and the power consumption is 181 mw.

scholarly journals Receiver Designs for Electronic Toll Collection Systems : A Survey

2020 ◽  
pp. 576-581
Author(s):  
Rarika Ravi ◽  
Anu Assis
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Automatic Gain Control ◽  
Power Level ◽  
Cmos Technology ◽  
Electronic Toll Collection ◽  
Chip Area ◽  
Advantages And Disadvantages ◽  
Digitally Controlled ◽  
Toll Collection

<p>This paper discusses about different receiver designs adopted so far for various electronic toll collection systems. A comparative analysis based on the discussions is also provided. It shows that each design has it's own advantages and disadvantages compared to others. The main aim of this paper is to identify the most suitable design. The researches shows that the receiver design described in the 5.8GHz digitally controlled DSRC receiver for Chinese electronic toll collection system is the most suitable one. Here all RF, IF blocks and digital baseband for on-chip automatic gain control, are integrated on an RF-SoC. The proposed digitally controlled LNA and mixer circuits are elaborated. The technology used is 0.13μm CMOS technology. The RF block occupies a chip area of 0.75mm2. It consumes 22mA under a 1.5V supply voltage. The bit error rate maintains better than 10-6, the input power level varies from -75dBm to -8dBm. This design provides a receiver sensitivity improvement of at least 25%, and a dynamic range enhancement of at least 12%.</p>

Wireless Interface at 5.7 GHz for Intra-Vehicle Communications

2012 ◽  
pp. 40-60
Author(s):  
J. P. Carmo ◽  
J. H. Correia
Keyword(s):  
Channel Capacity ◽  
Carrier Frequency ◽  
Spectrum Allocation ◽  
Total Power ◽  
Cmos Process ◽  
Rf Cmos ◽  
Rf Transceiver ◽  
Total Power Consumption ◽  
Multiple Frequencies ◽  
Wireless Interface

This chapter presents a wireless interface for intra-vehicle communications (data acquisition from sensors, control, and multimedia) at 5.7 GHz. As part of the wireless interface, a RF transceiver was fabricated in the UMC 0.18 µm RF CMOS process and when activated, it presents a total power consumption of 23 mW with the voltage-supply of 1.5 V. This allows the use of only a coin-sized battery for supplying the interface. The carrier frequency can be digitally selectable and take one of 16 possible frequencies in the range 5.42-5.83 GHz, adjusted in steps of 27.12 MHz. These multiple carriers allow a better spectrum allocation and at the same time will improve the channel capacity due to the possibility to allow multiple accesses with multiple frequencies.

scholarly journals None Operational Amplifier (OPA) Based: Design of Analogous Bandgap Reference Voltage

2018 ◽  
Vol 201 ◽  
pp. 02002
Author(s):  
Hao-Ping Chan ◽  
Yu-Cherng Hung
Keyword(s):  
Temperature Coefficient ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Chip Design ◽  
Chip Area ◽  
Voltage Variation ◽  
Current Variation

By using 0.35-um CMOS process, this work achieves a design of analogous band-gap reference voltage circuit with low temperature coefficient. The proposed circuit operates at 3V and generates a reference current of 44 uA. The HSPICE simulation results show the temperature coefficient of this circuit is 23 ppm/°C at range of -10 °C to 100 °C, and the line regulation (the ratio of output current variation to supply voltage variation) is estimated as 1.95 uA/V from supply voltage variation of 3 V to 5 V. The experimental chip is fabricated and measured. The circuit provides adjustable capability for output voltage among temperature variation of -10 - 100 °C. The chip area is 534 × 695 um2. In this new design, the operational amplifier is not necessary. The chip design effort can be great reduced.

2.2–4.6-GHz Active Quasi-Circulator with > 24-dB Transmit–Receive Isolation

2019 ◽  
Vol 29 (05) ◽  
pp. 2050077
Author(s):  
Najam Muhammad Amin ◽  
Lianfeng Shen ◽  
Danish Kaleem ◽  
Zhi-Gong Wang ◽  
Keping Wang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
The Body ◽  
Common Source ◽  
Cmos Process ◽  
Secondary Effects ◽  
Body Effect ◽  
Chip Area ◽  
Common Gate ◽  
Loading Effects ◽  
Better Than

An active quasi-circulator (AQC) integrated circuit is designed and fabricated in a 0.18-[Formula: see text]m CMOS process. The proposed design is based on a parallel combination of a common-source (CS) stage and a combined common-drain (CD) and common-gate (CG) topology. Scattering matrix of the core AQC circuit is derived considering MOSFET’s secondary effects, particularly the body effect as well as output loading effects. Measurements of the quasi-circulator reveal an insertion loss of [Formula: see text] dB between transmitter-to-antenna ports ([Formula: see text]) and of [Formula: see text] dB between antenna-to-receiver ports ([Formula: see text]), within a frequency band of 2.2–4.6 GHz. The isolation between the transmitter and the receiver ports ([Formula: see text]) is better than 24 dB with a maximum value of 29.5[Formula: see text]dB @ 3.6[Formula: see text]GHz. The power dissipation of the proposed AQC is 40[Formula: see text]mW and it covers an active chip area of 0.677[Formula: see text]mm2.

scholarly journals DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW

2019 ◽  
Vol 82 (1) ◽  
Author(s):  
Florence Choong ◽  
Mamun Ibne Reaz ◽  
Mohamad Ibrahim Kamaruzzaman ◽  
Md. Torikul Islam Badal ◽  
Araf Farayez ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Process Technology ◽  
Chip Area ◽  
Digital Phase ◽  
Low Power Dissipation

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL.

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