scholarly journals A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems

Sensors ◽  
2019 ◽  
Vol 20 (1) ◽  
pp. 171 ◽  
Author(s):  
Duckhoon Ro ◽  
Changhong Min ◽  
Myounggon Kang ◽  
Ik Joon Chang ◽  
Hyung-Min Lee
Keyword(s):  
Computer Aided Design ◽  
Power Plants ◽  
Radiation Effects ◽  
High Reliability ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Effective Control ◽  
Readout System ◽  
Flip Flop ◽  
Radiation Hardened

For stable and effective control of the sensor system, analog sensor signals such as temperature, pressure, and electromagnetic fields should be accurately measured and converted to digital bits. However, radiation environments, such as space, flight, nuclear power plants, and nuclear fusion reactors, as well as high-reliability applications, such as automotive semiconductor systems, suffer from radiation effects that degrade the performance of the sensor readout system including analog-to-digital converters (ADCs) and cause system malfunctions. This paper investigates an optimal ADC structure in radiation environments and proposes a successive- approximation-register (SAR) ADC using delay-based double feedback flip-flops to enhance the system tolerance against radiation effects, including total ionizing dose (TID) and single event effects (SEE). The proposed flip-flop was fabricated using 130 nm complementary metal–oxide–semiconductor (CMOS) silicon-on-insulator (SOI) process, and its radiation tolerance was measured in actual radiation test facilities. Also, the proposed radiation-hardened SAR ADC with delay-based dual feedback flip-flops was designed and verified by utilizing compact transistor models, which reflect radiation effects to CMOS parameters, and radiation simulator computer aided design (CAD) tools.

scholarly journals New Radiation-Hardened Design of a CMOS Instrumentation Amplifier and its Tolerant Characteristic Analysis

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 388 ◽  
Author(s):  
Minwoong Lee ◽  
Seongik Cho ◽  
Namho Lee ◽  
Jongyeol Kim
Keyword(s):  
Integrated Circuits ◽  
Nuclear Power ◽  
Power Plants ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Negative Effects ◽  
Characteristic Analysis ◽  
Radiation Hardened

A radiation-hardened instrumentation amplifier (IA) that allows precise measurement in radiation environments, including nuclear power plants, space environments, and radiation therapy rooms, was designed and manufactured, and its characteristics were verified. Most electronic systems are currently designed using silicon-based complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs) to achieve a highly integrated low-power design. However, fixed charges induced in silicon by ionization radiation cause various negative effects, resulting in, for example, the generation of leakage current in circuits, performance degradation, and malfunction. Given that such problems in radiation environments may directly lead to a loss of life or environmental contamination, it is critical to implement radiation-hardened CMOS IC technology. In this study, an IA used to amplify fine signals of the sensors was designed and fabricated in the 0.18 μm CMOS bulk process. The IA contained sub-circuits that ensured the stable voltage supply needed to implement system-on-chip (SoC) solutions. It was also equipped with special radiation-hardening technology by applying an I-gate n-MOSFET that blocks the radiation-induced leakage currents. Its ICs were verified to provide the intended performance following a total cumulative dose of up to 25 kGy(Si), ensuring its safety in radiation environments.

scholarly journals 3D Numerical Simulation of a Z Gate Layout MOSFET for Radiation Tolerance

Micromachines ◽  
2018 ◽  
Vol 9 (12) ◽  
pp. 659 ◽  
Author(s):  
Ying Wang ◽  
Chan Shan ◽  
Wei Piao ◽  
Xing-ji Li ◽  
Jian-qun Yang ◽  
...  
Keyword(s):  
Leakage Current ◽  
Threshold Voltage ◽  
Computer Aided Design ◽  
Oxide Semiconductor ◽  
Radiation Tolerance ◽  
Threshold Voltage Shift ◽  
Radiation Hardened ◽  
Small Footprint ◽  
Aided Design ◽  
First Time

In this paper, for the first time, an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) layout with a Z gate and an improved total ionizing dose (TID) tolerance is proposed. The novel layout can be radiation-hardened with a fixed charge density at the shallow trench isolation (STI) of 3.5 × 1012 cm−2. Moreover, it has the advantages of a small footprint, no limitation in W/L design, and a small gate capacitance compared with the enclosed gate layout. Beside the Z gate layout, a non-radiation-hardened single gate layout and a radiation-hardened enclosed gate layout are simulated using the Sentaurus 3D technology computer-aided design (TCAD) software. First, the transfer characteristics curves (Id-Vg) curves of the three layouts are compared to verify the radiation tolerance characteristic of the Z gate layout; then, the threshold voltage and the leakage current of the three layouts are extracted to compare their TID responses. Lastly, the threshold voltage shift and the leakage current increment at different radiation doses for the three layouts are presented and analyzed.

scholarly journals A Soft-Error-Tolerant SAR ADC with Dual-Capacitor Sample-and-Hold Control for Sensor Systems

Sensors ◽  
2021 ◽  
Vol 21 (14) ◽  
pp. 4768
Author(s):  
Duckhoon Ro ◽  
Minseong Um ◽  
Hyung-Min Lee
Keyword(s):  
Radiation Effects ◽  
Sar Adc ◽  
Soft Error ◽  
Fusion Reactors ◽  
Cmos Process ◽  
Readout System ◽  
Analog To Digital ◽  
Sample And Hold ◽  
Sensor Signals ◽  
Circuit Techniques

For a reliable and stable sensor system, it is essential to precisely measure various sensor signals, such as electromagnetic field, pressure, and temperature. The measured analog signal is converted into digital bits through the sensor readout system. However, in extreme radiation environments, such as in space, during flights, and in nuclear fusion reactors, the performance of the analog-to-digital converter (ADC) constituting the sensor readout system can be degraded due to soft errors caused by radiation effects, leading to system malfunction. This paper proposes a soft-error-tolerant successive-approximation-register (SAR) ADC using dual-capacitor sample-and-hold (S/H) control, which has robust characteristics against total ionizing dose (TID) and single event effects (SEE). The proposed ADC was fabricated using 65-nm CMOS process, and its soft-error-tolerant performance was measured in radiation environments. Additionally, the proposed circuit techniques were verified by utilizing a radiation simulator CAD tool.

scholarly journals A Radiation-Hardened Instrumentation Amplifier for Sensor Readout Integrated Circuits in Nuclear Fusion Applications

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 429 ◽  
Author(s):  
Kyungsoo Jeong ◽  
Duckhoon Ro ◽  
Gwanho Lee ◽  
Myounggon Kang ◽  
Hyung-Min Lee
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Radiation Effects ◽  
Nuclear Fusion ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Readout Integrated Circuit ◽  
Nuclear Fusion Reactor ◽  
Radiation Hardened

A nuclear fusion reactor requires a radiation-hardened sensor readout integrated circuit (IC), whose operation should be tolerant against harsh radiation effects up to MGy or higher. This paper proposes radiation-hardening circuit design techniques for an instrumentation amplifier (IA), which is one of the most sensitive circuits in the sensor readout IC. The paper studied design considerations for choosing the IA topology for radiation environments and proposes a radiation-hardened IA structure with total-ionizing-dose (TID) effect monitoring and adaptive reference control functions. The radiation-hardened performance of the proposed IA was verified through model-based circuit simulations by using compact transistor models that reflected the TID effects into complementary metal–oxide–semiconductor (CMOS) parameters. The proposed IA was designed with the 65 nm standard CMOS process and provides adjustable voltage gain between 3 and 15, bandwidth up to 400 kHz, and power consumption of 34.6 μW, while maintaining a stable performance over TID effects up to 1 MGy.

Design and Comparison of High-Reliable Radiation-Hardened Flip-Flops Under SMIC 40nm Process

2016 ◽  
Vol 25 (12) ◽  
pp. 1650163 ◽  
Author(s):  
Bingbing Xia ◽  
Jun Wu ◽  
Hongjin Liu ◽  
Kai Zhou ◽  
Zhifu Miao
Keyword(s):  
High Performance ◽  
High Reliability ◽  
Soft Error ◽  
Advanced Technology ◽  
Flip Flop ◽  
Aerospace Applications ◽  
Technology Process ◽  
Radiation Hardened ◽  
Power Radiation ◽  
Error Robustness

With the need for fast and low-power radiation-hardened processors, advanced technology process is applied to obtain both high performance as well as high reliability. However, scaling down of the size of the transistor makes the transistor sensitive to outside disturbances, such as soft error introduced by the strikes of the cosmic neutron beams. Besides aerospace applications, such reliability should also be taken into consideration for the sub-100[Formula: see text]nm CMOS designs to ensure the robustness of the circuit. In such circumstances, several radiation-hardened flip-flops are designed and simulated under SMIC 40[Formula: see text]nm process. Simulation results show that with five aspects (performance, power, area, PVT variation and reliability) taken into consideration, TSPC-based DICE and TMR combined architecture has the best soft-error robustness in comparison with other radiation-hardened flip-flops, and the critical charge of such architecture is 490[Formula: see text]fC, which is 12.5X higher than the traditional unhardened flip-flop.

scholarly journals Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

Sensors ◽  
2020 ◽  
Vol 20 (10) ◽  
pp. 2765 ◽  
Author(s):  
Changyeop Lee ◽  
Gyuseong Cho ◽  
Troy Unruh ◽  
Seop Hur ◽  
Inyong Kwon
Keyword(s):  
Metal Oxide ◽  
Integrated Circuit ◽  
Power Plants ◽  
Gate Oxide ◽  
Design Guidelines ◽  
Metal Oxide Semiconductor ◽  
Radiation Hardening ◽  
Oxide Semiconductor ◽  
Charge Sensitive Amplifier ◽  
Radiation Hardened

According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

"Recent Patents on the Triboelectrostatic Separation of Fly Ash"

2019 ◽  
Vol 13 ◽  
Author(s):  
Haisheng Li ◽  
Wenping Wang ◽  
Yinghua Chen ◽  
Xinxi Zhang ◽  
Chaoyong Li
Keyword(s):  
Fly Ash ◽  
Power Plants ◽  
High Efficiency ◽  
Separation Efficiency ◽  
High Reliability ◽  
Operating Conditions ◽  
Security Requirements ◽  
Unburned Carbon ◽  
Efficient Operation ◽  
Triboelectrostatic Separation

Background: The fly ash produced by coal-fired power plants is an industrial waste. The environmental pollution problems caused by fly ash have been widely of public environmental concern. As a waste of recoverable resources, it can be used in the field of building materials, agricultural fertilizers, environmental materials, new materials, etc. Unburned carbon content in fly ash has an influence on the performance of resource reuse products. Therefore, it is the key to remove unburned carbon from fly ash. As a physical method, triboelectrostatic separation technology has been widely used because of obvious advantages, such as high-efficiency, simple process, high reliability, without water resources consumption and secondary pollution. Objective: The related patents of fly ash triboelectrostatic separation had been reviewed. The structural characteristics and working principle of these patents are analyzed in detail. The results can provide some meaningful references for the improvement of separation efficiency and optimal design. Methods: Based on the comparative analysis for the latest patents related to fly ash triboelectrostatic separation, the future development is presented. Results: The patents focused on the charging efficiency and separation efficiency. Studies show that remarkable improvements have been achieved for the fly ash triboelectrostatic separation. Some patents have been used in industrial production. Conclusion: According to the current technology status, the researches related to process optimization and anti-interference ability will be beneficial to overcome the influence of operating conditions and complex environment, and meet system security requirements. The intelligent control can not only ensure the process continuity and stability, but also realize the efficient operation and management automatically. Meanwhile, the researchers should pay more attention to the resource utilization of fly ash processed by triboelectrostatic separation.

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

Nonvolatile Spin-Based Radiation Hardened Retention Latch and Flip-Flop

2019 ◽  
Vol 18 ◽  
pp. 1089-1096 ◽  
Author(s):  
Abdolah Amirany ◽  
Fahimeh Marvi ◽  
Kian Jafari ◽  
Ramin Rajaei
Keyword(s):  
Flip Flop ◽  
Radiation Hardened

scholarly journals Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1572
Author(s):  
Ehab A. Hamed ◽  
Inhee Lee
Keyword(s):  
Soft Error ◽  
Error Tolerance ◽  
Cmos Process ◽  
Flip Flop ◽  
Single Event Upsets ◽  
Area Overhead ◽  
Fair Comparison ◽  
Reference Design ◽  
Radiation Hardened ◽  
Radiation Hardened By Design

In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs). Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay. In this review, previously presented RHBD FFs are classified into three categories with an overview of each category. Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop (TGFF) is used as a reference design for this comparison. The results of the comparison are analyzed to give some important highlights about each design.

Sign in / Sign up

Export Citation Format

Share Document