scholarly journals A Soft-Error-Tolerant SAR ADC with Dual-Capacitor Sample-and-Hold Control for Sensor Systems

Sensors ◽  
2021 ◽  
Vol 21 (14) ◽  
pp. 4768
Author(s):  
Duckhoon Ro ◽  
Minseong Um ◽  
Hyung-Min Lee
Keyword(s):  
Radiation Effects ◽  
Sar Adc ◽  
Soft Error ◽  
Fusion Reactors ◽  
Cmos Process ◽  
Readout System ◽  
Analog To Digital ◽  
Sample And Hold ◽  
Sensor Signals ◽  
Circuit Techniques

For a reliable and stable sensor system, it is essential to precisely measure various sensor signals, such as electromagnetic field, pressure, and temperature. The measured analog signal is converted into digital bits through the sensor readout system. However, in extreme radiation environments, such as in space, during flights, and in nuclear fusion reactors, the performance of the analog-to-digital converter (ADC) constituting the sensor readout system can be degraded due to soft errors caused by radiation effects, leading to system malfunction. This paper proposes a soft-error-tolerant successive-approximation-register (SAR) ADC using dual-capacitor sample-and-hold (S/H) control, which has robust characteristics against total ionizing dose (TID) and single event effects (SEE). The proposed ADC was fabricated using 65-nm CMOS process, and its soft-error-tolerant performance was measured in radiation environments. Additionally, the proposed circuit techniques were verified by utilizing a radiation simulator CAD tool.

Study of Split Capacitor DAC Mismatch and Calibration in SAR-ADC

2016 ◽  
Vol 26 (01) ◽  
pp. 1750003
Author(s):  
Yun Zhang ◽  
Yiqiang Zhao ◽  
Peng Dai
Keyword(s):  
Calibration Method ◽  
Sar Adc ◽  
Calibration Error ◽  
Cmos Process ◽  
Analog To Digital ◽  
Significant Performance ◽  
Performance Deterioration ◽  
Conventional Structure ◽  
Split Capacitor ◽  
Simulation Results

Mismatch and parasitic effects of bridge capacitors in successive-approximation-register analog-to-digital converter’s (SAR-ADC) split capacitor digital-to-analog conversion (DAC) cause a significant performance deterioration. This paper presents a nonlinearity analysis based on an analytical model, and a modified calibration method utilizing a pre-bias bridge capacitor is accordingly proposed. The proposed method, which uses three-segment split capacitor DAC structure, can effectively eliminate over-calibration error caused by conventional structure. To verify the technique, a 14-bit SAR-ADC has been designed in 0.35-[Formula: see text]m 2P4M CMOS process with the PIP capacitor, and the simulation results show the method can further improve ADC performance.

scholarly journals A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 305 ◽  
Author(s):  
Dong Wang ◽  
Xiaoge Zhu ◽  
Xuan Guo ◽  
Jian Luan ◽  
Lei Zhou ◽  
...  
Keyword(s):  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Power Measurement ◽  
Cmos Process ◽  
Analog To Digital ◽  
Full Speed ◽  
Time Interleaved

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.

scholarly journals Modeling of High-Resolution Data Converter: Two-Step Pipelined-SAR ADC based on ISDM

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 137 ◽  
Author(s):  
Bo Gao ◽  
Xin Li ◽  
Jie Sun ◽  
Jianhui Wu
Keyword(s):  
High Resolution ◽  
Low Noise ◽  
Sar Adc ◽  
Total Power ◽  
Cmos Process ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Signal To Noise ◽  
Analog To Digital ◽  
High Bandwidth

The features of high-resolution and high-bandwidth are in an increasing demand considering to the wide range application fields based on high performance data converters. In this paper, a modeling of high-resolution hybrid analog-to-digital converter (ADC) is proposed to meet those requirements, and a 16-bit two-step pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with first-order continuous-time incremental sigma-delta modulator (ISDM) assisted is presented to verify this modeling. The combination of high-bandwidth two-step pipelined-SAR ADC with low noise ISDM and background comparator offset calibration can achieve higher signal-to-noise ratio (SNR) without sacrificing the speed and plenty of hardware. The usage of a sub-ranging scheme consists of a coarse SAR ADC followed by an fine ISDM, can not only provide better suppression of the noise added in 2nd stage during conversion but also alleviate the demands of comparator’s resolution in both stages for a given power budget, compared with a conventional Pipelined-SAR ADC. At 1.2 V/1.8 V supply, 33.3 MS/s and 16 MHz input sinusoidal signal in the 40 nm complementary metal oxide semiconductor (CMOS) process, the post-layout simulation results show that the proposed hybrid ADC achieves a signal-to-noise distortion ratio (SNDR) and a spurious free dynamic range (SFDR) of 86.3 dB and 102.5 dBc respectively with a total power consumption of 19.2 mW.

100 MS/s, 10-BIT ADC USING PIPELINED SUCCESSIVE APPROXIMATION

2014 ◽  
Vol 23 (05) ◽  
pp. 1450057
Author(s):  
SAHAR SARAFI ◽  
KHEYROLLAH HADIDI ◽  
EBRAHIM ABBASPOUR ◽  
ABU KHARI BIN AAIN ◽  
JAVAD ABBASZADEH
Keyword(s):  
Successive Approximation ◽  
Sar Adc ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Process Technology ◽  
Total Conversion ◽  
Analog To Digital ◽  
Simulation Results

This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined SAR-ADC's speed. The proposed method reduces the total conversion without limiting the ADC performance. To evaluate the proposed method a 10-bit 100 MS/s is designed in 0.5 μm CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 9-MHz input with 54.19 dB SNDR while consuming 57.3 mw from a 5-V supply.

scholarly journals Design of Bootstrap Sample and Hold Circuit

2019 ◽  
Vol 8 (4) ◽  
pp. 4053-4057
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Performance Metrics ◽  
Open Loop ◽  
Cmos Process ◽  
Bootstrap Sample ◽  
Analog To Digital ◽  
Sample And Hold ◽  
Higher Power ◽  
The Cost

This paper describes the design and implementation of open loop sample and hold circuit using bootstrap technique, which can be used as front end sampling circuit for high speed analog-to-digital converters. Different design criteria viz. speed, power, resolution, linearity, noise and harmonic analysis have been dealt with. Both theoretical analysis and simulation results are carried out. The bootstrap circuit is designed and then compared in a 0.18μm and 0.35μm CMOS process. It is observed that signal to noise and distortion ratio (SNDR) and effective number of bits (ENOB) are higher for 0.35µm technology. But these advantages are at the cost of higher power dissipation. Hence there exists a trade-off between these performance metrics.

scholarly journals A Mixed-Signal Programmable Time-Division Power-On-Reset and Volume Control Circuit for High-Resolution Hearing-Aid SoC Application

2018 ◽  
Vol 2018 ◽  
pp. 1-7
Author(s):  
Chengying Chen ◽  
Liming Chen ◽  
Jun Yang
Keyword(s):  
Low Power ◽  
Control Function ◽  
Hearing Aid ◽  
Sar Adc ◽  
Volume Control ◽  
Cmos Process ◽  
Mixed Signal ◽  
Analog To Digital ◽  
Power Application ◽  
Time Division

A mixed-signal programmable Time-Division Power-On-Reset (TD-POR) circuit based on 8-bit Successive Approximation Analog-to-Digital Converter (SAR ADC) for accurate control in low-power hearing-aid System on Chip (SoC) is presented in this paper. The end-of-converter (EOC) signal of SAR ADC is used as the mode-change signal so that the circuit can detect the battery voltage and volume voltage alternately. And the TD-POR circuit also has brown-out reset (BOR) detection capability. Through digital logic circuit, the POR, BOR threshold, and delay time can be adjusted according to the system requirement. The circuit is implemented in SMIC 0.13 μm 1P8M CMOS process. The measurement results show that, in 1 V power supply, the POR, BOR, and volume control function are accomplished. The detection resolution is the best among previous work. With 120 Hz input signal and 15 kHz clock, the ADC shows that Signal to Noise plus Distortion Ratio (SNDR) is 46.5 dB and Effective Number Of Bits (ENOB) is 7.43 bits. Total circuit power consumption is only 86 μw for low-power application.

scholarly journals High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit

2018 ◽  
Vol 8 (6) ◽  
pp. 4148
Author(s):  
Agung Setiabudi ◽  
Hiroki Tamura ◽  
Koichi Tanno
Keyword(s):  
Power Consumption ◽  
Input Signal ◽  
High Speed ◽  
Charge Injection ◽  
Cmos Process ◽  
Digital Converter ◽  
Analog To Digital ◽  
Differential Input ◽  
Transmission Gate ◽  
Sample And Hold

<p>A new high speed, low pedestal error bootstrapped CMOS sample and hold (S/H) circuit is proposed for high speed analog-to-digital converter (ADC). The proposed circuit is made up of CMOS transmission gate (TG) switch and two new bootstrap circuits for each transistor in TG switch. Both TG switch and bootstrap circuits are used to decrease channel charge injection and on-resistance input signal dependency. In result, distortion can be reduced. The decrease of channel charge injection input signal dependency also makes the minimizing of pedestal error by adjusting the width of NMOS and PMOS of TG switch possible. The performance of the proposed circuit was evaluated using HSPICE 0.18-m CMOS process. For 50 MHz sinusoidal 1 V peak-to-peak differential input signal with a 1 GHz sampling clock, the proposed circuit achieves 2.75 mV maximum pedestal error, 0.542 mW power consumption, 90.87 dB SNR, 73.50 SINAD which is equal to 11.92 bits ENOB, -73.58 dB THD, and 73.95 dB SFDR.</p>

scholarly journals A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

Electronics ◽  
2021 ◽  
Vol 10 (22) ◽  
pp. 2856
Author(s):  
Fang Tang ◽  
Qiyun Ma ◽  
Zhou Shu ◽  
Yuanjin Zheng ◽  
Amine Bermak
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Sar Adc ◽  
Cmos Process ◽  
Power Switching ◽  
Analog To Digital ◽  
Protection Scheme ◽  
Area Efficiency ◽  
Asynchronous Sar ◽  
28 Nm

This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm2. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/−0.44 and +0.48/−0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step.

scholarly journals A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology

2021 ◽  
Vol 15 ◽  
pp. 556-568
Author(s):  
Chaya Shetty ◽  
M. Nagabushanam ◽  
Venkatesh Nuthan Prasad
Keyword(s):  
High Speed ◽  
Signal To Noise Ratio ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Sar Adc ◽  
Cmos Process ◽  
Digital To Analog Converter ◽  
Additional Advantage ◽  
Analog To Digital ◽  
Split Capacitor

The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSATS-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design. The proposed switching technique of the (DSATS-CDAC) consumes less switching energy. Additionally, bootstrap switching is employed to ensure improved linearity and reduced power consumption.in order to enhance the speed of operation and increase the precision a preamplifier latch based comparator is implemented with the delay of 250ps. The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. The proposed design achieves a figure of merit (FOM) of 37.43 fJ/conversion-step, signal-to-noise-ratio (SNR) of 81 dB, and an effective-number-of-bits (ENOB) of 13.16 bits with a sampling rate of 125MS/s.

scholarly journals A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems

Sensors ◽  
2019 ◽  
Vol 20 (1) ◽  
pp. 171 ◽  
Author(s):  
Duckhoon Ro ◽  
Changhong Min ◽  
Myounggon Kang ◽  
Ik Joon Chang ◽  
Hyung-Min Lee
Keyword(s):  
Computer Aided Design ◽  
Power Plants ◽  
Radiation Effects ◽  
High Reliability ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Effective Control ◽  
Readout System ◽  
Flip Flop ◽  
Radiation Hardened

For stable and effective control of the sensor system, analog sensor signals such as temperature, pressure, and electromagnetic fields should be accurately measured and converted to digital bits. However, radiation environments, such as space, flight, nuclear power plants, and nuclear fusion reactors, as well as high-reliability applications, such as automotive semiconductor systems, suffer from radiation effects that degrade the performance of the sensor readout system including analog-to-digital converters (ADCs) and cause system malfunctions. This paper investigates an optimal ADC structure in radiation environments and proposes a successive- approximation-register (SAR) ADC using delay-based double feedback flip-flops to enhance the system tolerance against radiation effects, including total ionizing dose (TID) and single event effects (SEE). The proposed flip-flop was fabricated using 130 nm complementary metal–oxide–semiconductor (CMOS) silicon-on-insulator (SOI) process, and its radiation tolerance was measured in actual radiation test facilities. Also, the proposed radiation-hardened SAR ADC with delay-based dual feedback flip-flops was designed and verified by utilizing compact transistor models, which reflect radiation effects to CMOS parameters, and radiation simulator computer aided design (CAD) tools.

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