scholarly journals Affordable Thin Lens Using Single Polarized Disparate Filter Arrays for Beyond 5G toward 6G

Sensors ◽  
2019 ◽  
Vol 19 (18) ◽  
pp. 3982
Author(s):  
Inseop Yoon ◽  
Seongwoog Oh ◽  
Jungsuek Oh
Keyword(s):  
Manufacturing Process ◽  
Printed Circuit Board ◽  
Design Procedure ◽  
Circuit Board ◽  
Process Conditions ◽  
60 Ghz ◽  
Thin Lens ◽  
Gain Enhancement ◽  
Unit Cells ◽  
Pcb Manufacturing

This paper proposes a novel design approach for a thin lens with the aim of overcoming fineness limits in the commercial millimeter wave printed circuit board (PCB) manufacturing process. The PCB manufacturing process typically does not allow the fabrication of metallic patterns with a gap and width of less than 100 μm. This hampers expanding thin lens technology to 5G commercial applications, especially when such technology is considered for 60 GHz or higher frequency, which requires a finer gap and width of metallic traces. This paper proposes that problematic process conditions can be mitigated when a lens is designed by establishing single-polarized lumped element models where larger capacitance and inductance values can be obtained for the same patch and grid unit cells. While the proposed design technique is more advantageous at higher target frequencies, a 60 GHz application and a wireless backhaul system is selected because of a limited range of frequencies that can be measured by an available vector network analyzer. The required gap or width of metallic traces can be widened significantly by using the proposed single-polarized unit cells to acquire the same in-plane capacitance or inductance. This enables the lens operating at higher-frequency under the process limits in fabricable fine traces. Finally, the effectiveness of the simulated design procedure is demonstrated by fabricating a 60 GHz thin lens that can achieve a gain enhancement of 16 dB for a 4 × 4 patch antenna array with a gain of 16.5 dBi.

scholarly journals A Low-Cost and Efficient Microstrip-Fed Air-Substrate-Integrated Waveguide Slot Array

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 338
Author(s):  
Linfeng Li ◽  
Jie-Bang Yan
Keyword(s):  
Printed Circuit Board ◽  
High Efficiency ◽  
Low Cost ◽  
Design Procedure ◽  
Substrate Material ◽  
Circuit Board ◽  
Substrate Integrated Waveguide ◽  
Printed Circuit ◽  
Waveguide Transition ◽  
Pcb Manufacturing

A microstrip-fed air-substrate-integrated waveguide (ASIW) slot array with high efficiency and low cost is presented. The design cuts out the substrate material within SIW, replaces the vias with metallic sidewalls, and uses a simple microstrip line-waveguide transition to feed the slot array. Radiating slots are cut on a 5-mil brass-plate, which covers the top of the substrate cutout to resemble a hollow waveguide structure. This implementation provides a simple and efficient antenna array solution for millimeter-wave (mm-wave) applications. Meanwhile, the fabrication is compatible with the standard printed circuit board (PCB) manufacturing process. To demonstrate the concept, a 4-element ASIW slot array working at the n257 band for 5G communications was designed using low-cost Rogers 4350B and FR4 substrate materials. Our simulation result shows 18% more efficiency than a conventional SIW slot array using the same substrate. The fabricated prototype shows |S11| < −15 dB over 27–29 GHz and a peak realized gain of 10.1 dBi at 28.6 GHz. The design procedure, prototyping process, and design analysis are discussed in the paper.

The Die Embedded and RDL structure on the high density substrate (i-THOP®) for mobile application

2016 ◽  
Vol 2016 (1) ◽  
pp. 000001-000006
Author(s):  
Masahiro Kyozuka ◽  
Tatsuro Yoshida ◽  
Noriyoshi Shimizu ◽  
Koichi Tanaka ◽  
Tetsuya Koyama
Keyword(s):  
Mobile Devices ◽  
Manufacturing Process ◽  
Printed Circuit Board ◽  
Semiconductor Device ◽  
Current Trend ◽  
High Density ◽  
Circuit Board ◽  
Fine Pitch ◽  
Package Size ◽  
Proper Material

Abstract The current trend in the electronics industry is one of increased computing performance, combined with a seemingly unending demand for portability and increased miniaturization; this is especially evident in the significant changes to the semiconductor device. To sustain the performance-improvement trend without increasing total cost, the partitioning of single die into a multi-chip architecture is widely studied in industry. These partitioned chips are then integrated into a single system-in-package (SiP). However, partitioning a single die into multiple split die causes two major challenges. The first is that it creates the need for very high density die to die interconnection. This interconnection is needed to provide enough routing density between the multiple die. Based on design studies, it believes that 2μm line and 2μm space is required in the package substrate. The second challenge is created by the increase in the overall die size. After partitioning the single die, each resulting smaller die must have its own I/O circuits, and effectively increases the total die area. This increase is a penalty, as mobile devices have a limited package size. When comparing a conventional package on package (PoP), the SiP requires a higher pin count with a finer pitch connection between the die and the memory. This finer pitch is needed to have enough I/Os, but within a limited package size to support mobile devices. To overcome these challenges, the structure of i-THOP® with POP pad, named “i-THOP® with Die embedded +ReDestribution Layer(RDL) structure”, has been developed. Herein, i-THOP® (integrated Thin film High density Organic Package) is a type of high-density substrate A key aspect to development of Die embedded +RDL is forming the multiple redistribution layers (RDL) over die and the fine pitch via connection. To achieve this, the proper material set was selected based on stress simulations and basic experiments. Regarding the manufacturing process, a conventional printed-circuit board (PCB) production line was used to minimize production cost. This article reports the manufacturing process and characteristics of the structure.

Effect of Manufacturing Process Parameters on Property Evolution of Printed Circuit Board Laminates

2012 ◽  
Author(s):  
Pradeep Lall ◽  
Vikalp Narayan ◽  
Jim Blanche ◽  
Mark Strickland
Keyword(s):  
Glass Transition ◽  
Transition Temperature ◽  
Glass Transition Temperature ◽  
Manufacturing Process ◽  
Printed Circuit Board ◽  
Statistical Significance ◽  
Circuit Board ◽  
Effect Of Temperature ◽  
Process Variables ◽  
Printed Circuit

The effect of temperature exposure encountered both during assembly and in fielded products, has a known influence on glass transition temperature of printed-circuit board (PCB) laminate materials. Printed circuit board laminates such as FR4 are composites of epoxy resin with woven fiberglass reinforcement. Interaction between manufacturing process variables that impact the changes in glass transition temperature (Tg) has been studied. The laminates studied have been broadly classified into high-Tg, and mid-Tg laminates. Different sets of reflow profiles were created by varying the process variables including, time above liquidus, peak temperature, ramp rate and cooling rate. The effect of multiple reflows encountered in normal assembly or board re-work has been studied by exposing the assemblies to multiple reflows between 2x–6x. Changes to the glass transition temperature have been classified by measurement of the glass transition temperature were measured via Thermo Mechanical Analysis (TMA). Statistical analysis of the variables has been used to determine the statistical significance of the measured changes for large populations.

scholarly journals 2D Gain Enhancement Based on Single-Layer SIW Corrugated Technique with Slot Array Feeder

2018 ◽  
Vol 2018 ◽  
pp. 1-6
Author(s):  
Mingtuan Lin ◽  
Chenglong Lin
Keyword(s):  
Reflection Coefficient ◽  
Printed Circuit Board ◽  
Single Layer ◽  
High Gain ◽  
Circuit Board ◽  
Design Complexity ◽  
Printed Circuit ◽  
Gain Enhancement ◽  
High Gain Antenna ◽  
The Common

Novel slot-array-based SIW corrugated technique is demonstrated to achieve 2D gain enhancement, namely, sharpening the beamwidths in both E-plane and H-plane. Compared to other metallic corrugated methods to realize 2D gain enhancement, the proposed design, with SIW grooves to reduce the beamwidth in E-plane and slot array to increase the directivity in H-plane, has a lower profile, weight, and design complexity, which can be easily fabricated with the common printed circuit board (PCB) technique. A prototype is designed and fabricated, with measurement presenting a low reflection coefficient less than −10 dB from 26.4 GHz to 28.2 GHz and an enhanced gain up to 18 dB. Overall, our proposed technique will be beneficial for the design of high-gain antenna in 5G wireless terminals.

Process Improvement Using Design by Experiments

1994 ◽  
Author(s):  
Hsien-chen Li ◽  
Fuyau Lin
Keyword(s):  
Process Improvement ◽  
Manufacturing Process ◽  
Printed Circuit Board ◽  
Fractional Factorial Design ◽  
Time Budget ◽  
Fractional Factorial ◽  
Circuit Board ◽  
Printed Circuit ◽  
Printed Circuit Board Manufacturing

Abstract This paper present an approach to apply Design by Experiments for process improvement with the objectives to minimize cost and shorten investigation time. A case study of PCB (Printed Circuit Board) manufacturing process is chosen to illustrate this approach. A Fractional Factorial Design by Experiment was performed due to the constraints of the time, budget, and resources.

scholarly journals Circularly Polarized Triband Printed Quasi-Yagi Antenna for Millimeter-Wave Applications

2015 ◽  
Vol 2015 ◽  
pp. 1-9 ◽  
Author(s):  
Dalia M. Elsheakh ◽  
Magdy F. Iskander
Keyword(s):  
Circular Polarization ◽  
Printed Circuit Board ◽  
Ground Plane ◽  
Axial Ratio ◽  
Circuit Board ◽  
Impedance Bandwidth ◽  
60 Ghz ◽  
Antenna Structure ◽  
Circularly Polarized ◽  
Yagi Antenna

This paper describes the design and development of a triband with circularly polarized quasi-Yagi antenna for ka-band and short range wireless communications applications. The proposed antenna consists of an integrated balun-fed printed dipole, parasitic folded dipole and a short strip, and a modified ground plane. The antenna structure, together with the parasitic elements, is designed to achieve circular polarization and triband operating at resonant frequencies of 13.5 GHz, 30 GHz, and 60 GHz. Antenna design was first simulated using HFSS ver.14, and the obtained results were compared with experimental measurements on a prototype developed on a single printed circuit board. Achieved characteristics include −10 dB impedance bandwidth at the desired bands, circular polarization axial ratioAR<3 dB, front to back ratio of 6 dB, gain value of about 4 dBi, and average radiation efficiency of 60%. The paper includes comparison between simulation and experimental results.

A Novel Low Cost Package for Radio Frequency Applications

2013 ◽  
Vol 135 (2) ◽  
Author(s):  
Sandeep Chaturvedi ◽  
Shiban K. Koul
Keyword(s):  
High Frequency ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Cost Effective ◽  
Circuit Board ◽  
Test Results ◽  
Printed Circuit ◽  
Pcb Manufacturing ◽  
Manufacturing Techniques ◽  
Commercial Applications

Design, fabrication, and test results of a novel 3-layer RF package using a commonly available high frequency laminate are presented in this paper. The developed package can be manufactured using standard multilayer printed circuit board (PCB) manufacturing techniques making it cost effective for commercial applications. The package exhibits excellent RF characteristics up to 6 GHz.

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