The Die Embedded and RDL structure on the high density substrate (i-THOP®) for mobile application

2016 ◽  
Vol 2016 (1) ◽  
pp. 000001-000006
Author(s):  
Masahiro Kyozuka ◽  
Tatsuro Yoshida ◽  
Noriyoshi Shimizu ◽  
Koichi Tanaka ◽  
Tetsuya Koyama

Abstract The current trend in the electronics industry is one of increased computing performance, combined with a seemingly unending demand for portability and increased miniaturization; this is especially evident in the significant changes to the semiconductor device. To sustain the performance-improvement trend without increasing total cost, the partitioning of single die into a multi-chip architecture is widely studied in industry. These partitioned chips are then integrated into a single system-in-package (SiP). However, partitioning a single die into multiple split die causes two major challenges. The first is that it creates the need for very high density die to die interconnection. This interconnection is needed to provide enough routing density between the multiple die. Based on design studies, it believes that 2μm line and 2μm space is required in the package substrate. The second challenge is created by the increase in the overall die size. After partitioning the single die, each resulting smaller die must have its own I/O circuits, and effectively increases the total die area. This increase is a penalty, as mobile devices have a limited package size. When comparing a conventional package on package (PoP), the SiP requires a higher pin count with a finer pitch connection between the die and the memory. This finer pitch is needed to have enough I/Os, but within a limited package size to support mobile devices. To overcome these challenges, the structure of i-THOP® with POP pad, named “i-THOP® with Die embedded +ReDestribution Layer(RDL) structure”, has been developed. Herein, i-THOP® (integrated Thin film High density Organic Package) is a type of high-density substrate A key aspect to development of Die embedded +RDL is forming the multiple redistribution layers (RDL) over die and the fine pitch via connection. To achieve this, the proper material set was selected based on stress simulations and basic experiments. Regarding the manufacturing process, a conventional printed-circuit board (PCB) production line was used to minimize production cost. This article reports the manufacturing process and characteristics of the structure.

2018 ◽  
Vol 193 (3-4) ◽  
pp. 578-584 ◽  
Author(s):  
Xavier de la Broïse ◽  
Alain Le Coguie ◽  
Jean-Luc Sauvageot ◽  
Claude Pigot ◽  
Xavier Coppolani ◽  
...  

Sensors ◽  
2019 ◽  
Vol 19 (18) ◽  
pp. 3982
Author(s):  
Inseop Yoon ◽  
Seongwoog Oh ◽  
Jungsuek Oh

This paper proposes a novel design approach for a thin lens with the aim of overcoming fineness limits in the commercial millimeter wave printed circuit board (PCB) manufacturing process. The PCB manufacturing process typically does not allow the fabrication of metallic patterns with a gap and width of less than 100 μm. This hampers expanding thin lens technology to 5G commercial applications, especially when such technology is considered for 60 GHz or higher frequency, which requires a finer gap and width of metallic traces. This paper proposes that problematic process conditions can be mitigated when a lens is designed by establishing single-polarized lumped element models where larger capacitance and inductance values can be obtained for the same patch and grid unit cells. While the proposed design technique is more advantageous at higher target frequencies, a 60 GHz application and a wireless backhaul system is selected because of a limited range of frequencies that can be measured by an available vector network analyzer. The required gap or width of metallic traces can be widened significantly by using the proposed single-polarized unit cells to acquire the same in-plane capacitance or inductance. This enables the lens operating at higher-frequency under the process limits in fabricable fine traces. Finally, the effectiveness of the simulated design procedure is demonstrated by fabricating a 60 GHz thin lens that can achieve a gain enhancement of 16 dB for a 4 × 4 patch antenna array with a gain of 16.5 dBi.


2008 ◽  
Vol 20 (12) ◽  
pp. 964-966 ◽  
Author(s):  
Byung Sup Rho ◽  
Woo-Jin Lee ◽  
Jung Woon Lim ◽  
Ki Young Jung ◽  
Kyung Soon Cha ◽  
...  

Author(s):  
Pradeep Lall ◽  
Vikalp Narayan ◽  
Jim Blanche ◽  
Mark Strickland

The effect of temperature exposure encountered both during assembly and in fielded products, has a known influence on glass transition temperature of printed-circuit board (PCB) laminate materials. Printed circuit board laminates such as FR4 are composites of epoxy resin with woven fiberglass reinforcement. Interaction between manufacturing process variables that impact the changes in glass transition temperature (Tg) has been studied. The laminates studied have been broadly classified into high-Tg, and mid-Tg laminates. Different sets of reflow profiles were created by varying the process variables including, time above liquidus, peak temperature, ramp rate and cooling rate. The effect of multiple reflows encountered in normal assembly or board re-work has been studied by exposing the assemblies to multiple reflows between 2x–6x. Changes to the glass transition temperature have been classified by measurement of the glass transition temperature were measured via Thermo Mechanical Analysis (TMA). Statistical analysis of the variables has been used to determine the statistical significance of the measured changes for large populations.


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