scholarly journals High-Q Wafer Level Package Based on Modified Tri-Layer Anodic Bonding and High Performance Getter and Its Evaluation for Micro Resonant Pressure Sensor

Sensors ◽  
2017 ◽  
Vol 17 (3) ◽  
pp. 599 ◽  
Author(s):  
Liying Wang ◽  
Xiaohui Du ◽  
Lingyun Wang ◽  
Zhanhao Xu ◽  
Chenying Zhang ◽  
...  
Keyword(s):  
Pressure Sensor ◽  
High Performance ◽  
Anodic Bonding ◽  
Wafer Level ◽  
High Q ◽  
Wafer Level Package

scholarly journals A High Q-Factor Outer-Frame-Anchor Gyroscope Operating at First Resonant Mode

Micromachines ◽  
2020 ◽  
Vol 11 (12) ◽  
pp. 1071
Author(s):  
Bo Jiang ◽  
Yan Su ◽  
Guowen Liu ◽  
Lemin Zhang ◽  
Fumin Liu
Keyword(s):  
High Performance ◽  
Microelectromechanical Systems ◽  
Resonant Mode ◽  
Low Noise ◽  
Silicon On Insulator ◽  
Q Factor ◽  
Wafer Level ◽  
High Q ◽  
Ring Structures ◽  
Static Performance

Disc gyroscope manufactured through microelectromechanical systems (MEMS) fabrication processes becomes one of the most critical solutions for achieving high performance. Some reported novel disc constructions acquire good performance in bias instability, scale factor nonlinearity, etc. However, antivibration characteristics are also important for the devices, especially in engineering applications. For multi-ring structures with central anchors, the out-of-plane motions are in the first few modes, easily excited within the vibration environment. The paper presents a multi-ring gyro with good dynamic characteristics, operating at the first resonant mode. The design helps obtain better static performance and antivibration characteristics with anchor points outside of the multi-ring resonator. According to harmonic experiments, the nearest interference mode is located at 30,311 Hz, whose frequency difference is 72.8% far away from working modes. The structures were fabricated with silicon on insulator (SOI) processes and wafer-level vacuum packaging, where the asymmetry is 780 ppm as the frequency splits. The gyro also obtains a high Q-factor. The measured value at 0.15 Pa was 162 k, which makes the structure have sizeable mechanical sensitivity and low noise.

A low phase noise LC-VCO with a high-Q inductor fabricated by wafer level package technology

2008 ◽  
Author(s):  
Kazuma Ohashi ◽  
Yuka Kobayashi ◽  
Hiroyuki Ito ◽  
Kenichi Okada ◽  
Hideki Hatakeyama ◽  
...  
Keyword(s):  
Phase Noise ◽  
Wafer Level ◽  
High Q ◽  
Wafer Level Package ◽  
Low Phase Noise ◽  
Lc Vco

Wafer Level Package for MEMS with TSVs and Hermetic Seal

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002314-002335
Author(s):  
Akinori Shiraishi ◽  
Mitsutoshi Higashi ◽  
Kei Murayama ◽  
Yuichi Taguchi ◽  
Kenichi Mori
Keyword(s):  
Silicon Wafer ◽  
Adhesive Bonding ◽  
Anodic Bonding ◽  
Back Side ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Mems Device ◽  
Bonding Method ◽  
Wafer Level Package

In recent years, downsizing of MEMS package and high accuracy MEMS device mounting have been strongly required from expanding applications that using MEMS not only for industrial and automobile but also for consumer typified mobile phone. In order to achieve that, it is appropriate to use Silicon package that can be mounted at wafer level packaging. Silicon package is made of monocrystal silicon wafer. The deep cavity is fabricated on monocrystal silicon wafer by Wet or Dry etching. And MEMS device can be mounted on the cavity. The electrical connecting between front side and back side of cavity portion is achieved by TSVs that located on the bottom of cavity. Hermetic seal can be achieved by using glass or silicon wafer bonding method. By using a driver device wafer (before dicing) as the cap for hermetic seal, smaller size and smaller number of parts module can be fabricated. In this report, methods and designs for hermetic seal with wafer level process were examined. Methods that applied were polyimide adhesive bonding, anodic bonding and Au-In solder bonding. Location of TSVs on the bottom of cavity and thickness of diaphragm with TSVs was also examined. Silicon package for piezo type gyro MEMS that designed by the result of evaluation was fabricated. This package used optimized Au-In solder bonding for hermetic seal and optimized location of TSVs for interconnection. That was designed over 50% thinner than conventional ceramic packages. Characteristics of hermetic seal were evaluated by Q factor of gyro MEMS that mounted inside of the silicon package. It is confirmed that performance of sealing are good enough for running of the MEMS.

Inductors from wafer-level package process for high performance RF applications

2009 ◽  
Author(s):  
Badakere Guruprasad ◽  
Yaojian Lin ◽  
M. Pandi Chelvam ◽  
Seung Wook Yoon ◽  
Kai Liu ◽  
...  
Keyword(s):  
High Performance ◽  
Wafer Level ◽  
Rf Applications ◽  
Wafer Level Package

scholarly journals Novel resonant pressure sensor based on piezoresistive detection and symmetrical in-plane mode vibration

2020 ◽  
Vol 6 (1) ◽  
Author(s):  
Xiangguang Han ◽  
Qi Mao ◽  
Libo Zhao ◽  
Xuejiao Li ◽  
Li Wang ◽  
...  
Keyword(s):  
Pressure Sensor ◽  
High Vacuum ◽  
Frequency Theory ◽  
Structure Design ◽  
Anodic Bonding ◽  
Wafer Level ◽  
Resonant Frequency Shift ◽  
Simulation And Experiment ◽  
Mode Stress ◽  
Full Temperature

AbstractIn this paper, a novel resonant pressure sensor is developed based on electrostatic excitation and piezoresistive detection. The measured pressure applied to the diaphragm will cause the resonant frequency shift of the resonator. The working mode stress–frequency theory of a double-ended tuning fork with an enhanced coupling beam is proposed, which is compatible with the simulation and experiment. A unique piezoresistive detection method based on small axially deformed beams with a resonant status is proposed, and other adjacent mode outputs are easily shielded. According to the structure design, high-vacuum wafer-level packaging with different doping in the anodic bonding interface is fabricated to ensure the high quality of the resonator. The pressure sensor chip is fabricated by dry/wet etching, high-temperature silicon bonding, ion implantation, and wafer-level anodic bonding. The results show that the fabricated sensor has a measuring sensitivity of ~19 Hz/kPa and a nonlinearity of 0.02% full scale in the pressure range of 0–200 kPa at a full temperature range of −40 to 80 °C. The sensor also shows a good quality factor >25,000, which demonstrates the good vacuum performance. Thus, the feasibility of the design is a commendable solution for high-accuracy pressure measurements.

FOWLP Technology as an Wafer Level System in Packaging (SiP) Solution

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-41 ◽  
Author(s):  
Lewis(In Soo) Kang
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Industrial Applications ◽  
System Control ◽  
Wafer Level ◽  
Communication Module ◽  
3D Packaging ◽  
Control Application ◽  
Wafer Level Package

The market of Connectivity, Internet of Things (IoT), Wearable and Smart industrial applications leads Fan Out Wafer Level Package (FOWLP) technologies to a promising solution to overcome the limitation of conventional wafer level package, flip chip package and wire bonding package in terms of the solution of low cost, high performance and smaller form factor packaging. Moreover, FOWLP technology can be extended to system-in-package (SiP) area, such as multi chip 2D package and 3D stack package types. nepes Corporation has developed several advanced package platforms such as single, multi dies and 2D, 3D packaging by using FOWLP and embedding technologies. To fulfill SiP (system-in-package) with FOWLP, several dies and components have been embedded into one package which offers 40~90 % of volumetric shrink compared to the current module system with the flexibility of product design for end users. 3D package technology of PoP (Package on Package) structure will be introduced for communication module and system control application.

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