scholarly journals Clean-Room Lithographical Processes for the Fabrication of Graphene Biosensors

Materials ◽  
2020 ◽  
Vol 13 (24) ◽  
pp. 5728
Author(s):  
Patrícia D. Cabral ◽  
Telma Domingues ◽  
George Machado ◽  
Alexandre Chicharo ◽  
Fátima Cerqueira ◽  
...  

This work is on developing clean-room processes for the fabrication of electrolyte-gate graphene field-effect transistors at the wafer scale for biosensing applications. Our fabrication process overcomes two main issues: removing surface residues after graphene patterning and the dielectric passivation of metallic contacts. A graphene residue-free transfer process is achieved by using a pre-transfer, sacrificial metallic mask that protects the entire wafer except the areas around the channel, source, and drain, onto which the graphene film is transferred and later patterned. After the dissolution of the mask, clean gate electrodes are obtained. The multilayer SiO2/SiNx dielectric passivation takes advantage of the excellent adhesion of SiO2 to graphene and the substrate materials and the superior impermeability of SiNx. It hinders native nucleation centers and breaks the propagation of defects through the layers, protecting from prolonged exposition to all common solvents found in biochemistry work, contrary to commonly used polymeric passivation. Since wet etch does not allow the required level of control over the lithographic process, a reactive ion etching process using a sacrificial metallic stopping layer is developed and used for patterning the passivation layer. The process achieves devices with high reproducibility at the wafer scale.

2018 ◽  
Vol 86 (2) ◽  
pp. 51-57
Author(s):  
Arul Vigneswar Ravichandran ◽  
Jaebeom Lee ◽  
Lanxia Cheng ◽  
Antonio Tomas Lucero ◽  
Chadwin D Young ◽  
...  

2022 ◽  
Vol 6 (1) ◽  
Author(s):  
Taikyu Kim ◽  
Cheol Hee Choi ◽  
Pilgyu Byeon ◽  
Miso Lee ◽  
Aeran Song ◽  
...  

AbstractAchieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.


2001 ◽  
Vol 665 ◽  
Author(s):  
A. Ullmann ◽  
J. Ficker ◽  
W. Fix ◽  
H. Rost ◽  
W. Clemens ◽  
...  

ABSTRACTIntegrated plastic circuits (IPCs) will become an integral component of future low cost electronics. For low cost processes IPCs have to be made of all-polymer Transistors. We present our recent results on fabrication of Organic Field-Effect Transistors (OFETs) and integrated inverters. Top-gate transistors were fabricated using polymer semiconductors and insulators. The source-drain structures were defined by standard lithography of Au on a flexible plastic film, and on top of these electrodes, poly(3-alkylthiophene) (P3AT) as semiconductor, and poly(4-hydroxystyrene) (PHS) as insulator were homogeneously deposited by spin-coating. The gate electrodes consist of metal contacts. With this simple set-up, the transistors exhibit excellent electric performance with a high source-drain current at source - drain and gate voltages below 30V. The characteristics show very good saturation behaviour for low biases and are comparable to results published for precursor pentacene. With this setup we obtain a mobility of 0.2cm2/Vs for P3AT. Furthermore, we discuss organic integrated inverters exhibiting logic capability. All devices show shelf-lives of several months without encapsulation.


2020 ◽  
Vol 41 (9) ◽  
pp. 1428-1431 ◽  
Author(s):  
V. R. Saran Kumar Chaganti ◽  
Tristan K. Truttmann ◽  
Fengdeng Liu ◽  
Bharat Jalan ◽  
Steven J. Koester

2020 ◽  
Vol 6 (9) ◽  
pp. 2000515
Author(s):  
Baolin Zhao ◽  
Bastian Gothe ◽  
Marco Sarcletti ◽  
Yuhan Zhao ◽  
Tobias Rejek ◽  
...  

Nanoscale ◽  
2016 ◽  
Vol 8 (4) ◽  
pp. 2268-2276 ◽  
Author(s):  
Philip M. Campbell ◽  
Alexey Tarasov ◽  
Corey A. Joiner ◽  
Meng-Yen Tsai ◽  
Georges Pavlidis ◽  
...  

2002 ◽  
Vol 81 (7) ◽  
pp. 1359-1359 ◽  
Author(s):  
S. J. Wind ◽  
J. Appenzeller ◽  
R. Martel ◽  
V. Derycke ◽  
Ph. Avouris

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