scholarly journals Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel

Electronics ◽  
2019 ◽  
Vol 8 (9) ◽  
pp. 988
Author(s):  
Seon ◽  
Kim ◽  
Kim ◽  
Jeon
Keyword(s):  
Crystalline Silicon ◽  
Boundary Effect ◽  
Nand Flash ◽  
Short Channel ◽  
Poly Silicon ◽  
Proposed Model ◽  
Current Voltage ◽  
Channel Effects ◽  
Long Time ◽  
Memory Applications

Poly-crystalline silicon channel transistors have been used as a display TFT for a long time and have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND upright. In addition, multi-gate transistors such as FinFETs and a gate-all-around (GAA) structure has been used to suppress the short-channel effects for logic/analog and memory applications. Compact models for poly-crystalline silicon (poly-silicon) channel planar TFTs and single crystalline silicon channel GAA MOSFETs have been developed separately, however, there are few models consider these two physics at the same time. In this work, we derived new analytical current-voltage model for GAA transistor with poly-silicon channel by considering the cylindrical coordinates and the grain boundary effect. Based on the derived formula, the compact I-V model for various operating regions and threshold voltage was proposed for the first time. The proposed model was compared with the measured data and good agreements were observed.

scholarly journals Potential and Quantum Threshold Voltage Modeling of Gate-All-Around Nanowire MOSFETs

2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
M. Karthigai Pandian ◽  
N. B. Balamurugan ◽  
A. Pricilla
Keyword(s):  
Threshold Voltage ◽  
Silicon Nanowire ◽  
Electrical Potential ◽  
Short Channel Effects ◽  
Short Channel ◽  
Weak Inversion ◽  
Silicon Devices ◽  
Proposed Model ◽  
Channel Effects ◽  
Quantum Mechanical Effects

An improved physics-based compact model for a symmetrically biased gate-all-around (GAA) silicon nanowire transistor is proposed. Short channel effects and quantum mechanical effects caused by the ultrathin silicon devices are considered in modelling the threshold voltage. Device geometrics play a very important role in multigate devices, and hence their impact on the threshold voltage is also analyzed by varying the height and width of silicon channel. The inversion charge and electrical potential distribution along the channel are expressed in their closed forms. The proposed model shows excellent accuracy with TCAD simulations of the device in the weak inversion regime.

Modeling of $V_{\rm th}$ Shift in nand Flash-Memory Cell Device Considering Crosstalk and Short-Channel Effects

2008 ◽  
Vol 55 (4) ◽  
pp. 1020-1026 ◽  
Author(s):  
Sang-Goo Jung ◽  
Keun-Woo Lee ◽  
Ki-Seog Kim ◽  
Seung-Woo Shin ◽  
Seaung-Suk Lee ◽  
...  
Keyword(s):  
Flash Memory ◽  
Memory Cell ◽  
Nand Flash ◽  
Short Channel Effects ◽  
Nand Flash Memory ◽  
Short Channel ◽  
Channel Effects ◽  
Flash Memory Cell

scholarly journals Analytical Current–Voltage Modeling and Analysis of the MFIS Gate-All-Around Transistor Featuring Negative-Capacitance

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1177
Author(s):  
Yeji Kim ◽  
Yoongeun Seon ◽  
Soowon Kim ◽  
Jongmin Kim ◽  
Saemin Bae ◽  
...  
Keyword(s):  
Ferroelectric Material ◽  
Compact Model ◽  
Design Parameters ◽  
Interface Trap ◽  
Negative Capacitance ◽  
Short Channel ◽  
Modeling And Analysis ◽  
Operating Region ◽  
Proposed Model ◽  
Current Voltage

Recently, in accordance with the demand for development of low-power semiconductor devices, a negative capacitance field-effect-transistor (NC-FET) that integrates ferroelectric material into a gate stack and utilizes negative capacitive behavior has been widely investigated. Furthermore, gate-all-around (GAA) architecture to reduce short-channel effect is expected to be applied after Fin-FET technology. In this work, we proposed a compact model describing current–voltage (I–V) relationships of an NC GAA-FET with interface trap effects for the first time, which is a simplified model by taking proper approximation in each operating region. This is a surface potential-based compact model, which is suitable for evaluating the I–V characteristics for each operating region. It was validated that the proposed model shows good agreement with the results of implicit numerical calculations. In addition, by using the proposed model, we explored the electrical properties of the NC GAA-FET by varying the basic design parameters such as ferroelectric thickness (tfe), intermediate insulator thickness (tox), silicon channel radius (R), and interface trap densities (Net).

scholarly journals A compact model of transconductance and drain conductance for DMG-GC-DOT cylindrical gate MOSFET

2020 ◽  
Vol 9 (1) ◽  
pp. 34
Author(s):  
Hind Jaafar ◽  
Abdellah Aouaj ◽  
Benjamin Iñiguez
Keyword(s):  
Compact Model ◽  
Short Channel Effects ◽  
Short Channel ◽  
The Core ◽  
Proposed Model ◽  
Channel Effects ◽  
Design Effectiveness ◽  
Silvaco Atlas ◽  
Dual Material ◽  
Drain Conductance

A compact model for dual-material gate graded-channel and dual-oxide<br />thickness with two dielectric constant different cylindrical gate (DMG-GC-<br />DOTTDCD) MOSFET was investigated in terms of transconductance, drain<br />conductance and capacitance. Short channel effects are modeled with simple<br />expressions, and incorporated into the core of the model (at the drain<br />current). The design effectiveness of DMG-GC-DOTTDCD was monitored<br />in comparing with the DMG-GC-DOT transistor, the effect of variations of<br />technology parameters, was presented in terms of gate polarization and drain<br />polarization. The results indicate that the DMG-GC-DOTTDCD devices<br />have characteristics higher than the DMG-GC-DOT MOSFET. To validate<br />the proposed model, we used the results obtained from the simulation of the<br />device with the SILVACO-ATLAS-TCAD software.

Monte Carlo study of 50 nm-long single and dual-gate MODFETs: suppression of short-channel effects

1993 ◽  
Vol 3 (9) ◽  
pp. 1719-1728
Author(s):  
P. Dollfus ◽  
P. Hesto ◽  
S. Galdin ◽  
C. Brisset
Keyword(s):  
Monte Carlo ◽  
Monte Carlo Study ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
Dual Gate

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

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