scholarly journals Low Cost Test Pattern Generation in Scan-Based BIST Schemes

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 314 ◽  
Author(s):  
Guohe Zhang ◽  
Ye Yuan ◽  
Feng Liang ◽  
Sufen Wei ◽  
Cheng-Fu Yang
Keyword(s):  
Test Pattern ◽  
Low Cost ◽  
Pattern Generator ◽  
Pattern Generation ◽  
Low Power Consumption ◽  
Test Pattern Generation ◽  
Hardware Overhead ◽  
Single Input ◽  
Simulation Results ◽  
Self Test

This paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes. Our method generates broadcast-based multiple single input change (BMSIC) vectors to fill more scan chains. The proposed algorithm, BMSIC-TPG, is based on our previous work multiple single-input change (MSIC)-TPG. The broadcast circuit expends MSIC vectors, so that the hardware overhead of the test pattern generation circuit is reduced. Simulation results with ISCAS’89 benchmarks and a comparison with the MSIC-TPG circuit show that the proposed BMSIC-TPG reduces the circuit hardware overhead about 50% with ensuring of low power consumption and high fault coverage.

A low power test pattern generation for built-in self-test based circuits

2011 ◽  
Vol 98 (3) ◽  
pp. 301-309 ◽  
Author(s):  
Bo Ye ◽  
Tianwang Li ◽  
Qian Zhao ◽  
Duo Zhou ◽  
Xiaohua Wang ◽  
...  
Keyword(s):  
Low Power ◽  
Test Pattern ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Power Test ◽  
Low Power Test ◽  
Self Test ◽  
Built In Self Test

A SIC PAIR GENERATOR FOR A BILBO ENVIRONMENT

2006 ◽  
Vol 15 (05) ◽  
pp. 739-756 ◽  
Author(s):  
I. VOYIATZIS ◽  
D. KEHAGIAS
Keyword(s):  
Test Pattern ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Practice Test ◽  
Logic Block ◽  
Efficient Alternative ◽  
Single Input ◽  
Self Test ◽  
On Chip ◽  
Cmos Vlsi

Built-In Self Test (BIST) techniques are commonly used as an efficient alternative to external testing in today's high-complexity VLSI chips since they provide on-chip test pattern generation and response verification. Among the BIST techniques, Built-In Logic Block Observation (BILBO) has been widely used in practice. Test patterns generated by BILBO structures target the detection of stuck-at faults. It has been shown that most common failure mechanisms that appear into current CMOS VLSI circuits cannot be modeled as stuck-at faults. These mechanisms, modeled by sequential (i.e., stuck-open and delay) faults models, require the application of two-pattern tests (vector pairs) in the circuit-under-test inputs. Single Input Change (SIC) pairs are pairs of patterns where the second pattern differs from the first in only one bit and have been successfully used for two-pattern testing. In this paper we present the BILBO-oriented SIC pair Generator technique that extends BILBO in order to generate SIC pairs; in this way, sequential faults are also detected.

Sign in / Sign up

Export Citation Format

Share Document