A test pattern generation methodology for low power consumption

2002 ◽  
Author(s):  
E. Corno ◽  
P. Prinetto ◽  
M. Rebaudengo ◽  
M.S. Reorda
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Pattern ◽  
Pattern Generation ◽  
Low Power Consumption ◽  
Test Pattern Generation

scholarly journals Test Pattern Generation with Low Power for Delay Faults in Digital Circuits by Evolution Method with Hybrid Strategies

2014 ◽  
Vol 8 (1) ◽  
pp. 77-83
Author(s):  
Pan Zhongliang ◽  
Chen Ling ◽  
Chen Yihui
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Digital Circuits ◽  
Test Pattern ◽  
Average Power ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Delay Faults ◽  
High Power Consumption ◽  
Test Vectors

The high power consumption during circuit test process can produce unwanted failures or take effects on circuit reliability, therefore the reduction of both peak power and average power of circuit test is necessary. A test pattern generation approach is presented in this paper for the delay faults in digital circuits, the approach makes use of the evolution method with the hybrid strategies to produce the test vectors with low power consumption. First of all, a pair of vectors that may detect a delay fault is coded as an individual. A lot of individuals constitute the populations. Secondly, the test vectors with low power are produced by the evolution of these populations. Many new individuals are randomly produced and are added into every evolution step, and the mutation mode of individuals is related to other individuals in the current population. A lot of experimental results show that the test vectors with low power for the delay faults in digital circuits can be produced by the approach proposed in this paper, and the approach can get the large reduction of power consumption when compared with random test generation algorithm.

scholarly journals An Efficient Test Pattern Generation Scheme for an On Chip BIST

VLSI Design ◽  
2001 ◽  
Vol 12 (4) ◽  
pp. 551-562 ◽  
Author(s):  
B. K. S. V. L. Varaprasad ◽  
L. M. Patnaik ◽  
H. S. Jamadagni ◽  
V. K. Agrawal
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Pattern ◽  
Circuit Simulation ◽  
Cost Effective ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Space Applications ◽  
Efficient Test ◽  
On Chip

Testing and power consumption are becoming two critical issues in VLSI design due to the growing complexity of VLSI circuits and remarkable success and growth of low power applications (viz. portable consumer electronics and space applications). On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip. This paper deals with cost-effective Test Pattern Generation (TPG) schemes in BIST. We present a novel methodology based on the use of a suitable Linear Feedback Shift Register (LFSR) which cycles through the required sequences (test vectors) aiming at a desired fault coverage causing minimum circuit toggling and hence low power consumption while testing. The proposed technique uses circuit simulation data for modeling. We show how to identify the LFSR using graph theory techniques and compute its feedback coefficients (i.e., its characteristic polynomial) for realization of a Test Pattern Generator.

A low power test pattern generation for built-in self-test based circuits

2011 ◽  
Vol 98 (3) ◽  
pp. 301-309 ◽  
Author(s):  
Bo Ye ◽  
Tianwang Li ◽  
Qian Zhao ◽  
Duo Zhou ◽  
Xiaohua Wang ◽  
...  
Keyword(s):  
Low Power ◽  
Test Pattern ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Power Test ◽  
Low Power Test ◽  
Self Test ◽  
Built In Self Test

scholarly journals Low Cost Test Pattern Generation in Scan-Based BIST Schemes

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 314 ◽  
Author(s):  
Guohe Zhang ◽  
Ye Yuan ◽  
Feng Liang ◽  
Sufen Wei ◽  
Cheng-Fu Yang
Keyword(s):  
Test Pattern ◽  
Low Cost ◽  
Pattern Generator ◽  
Pattern Generation ◽  
Low Power Consumption ◽  
Test Pattern Generation ◽  
Hardware Overhead ◽  
Single Input ◽  
Simulation Results ◽  
Self Test

This paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes. Our method generates broadcast-based multiple single input change (BMSIC) vectors to fill more scan chains. The proposed algorithm, BMSIC-TPG, is based on our previous work multiple single-input change (MSIC)-TPG. The broadcast circuit expends MSIC vectors, so that the hardware overhead of the test pattern generation circuit is reduced. Simulation results with ISCAS’89 benchmarks and a comparison with the MSIC-TPG circuit show that the proposed BMSIC-TPG reduces the circuit hardware overhead about 50% with ensuring of low power consumption and high fault coverage.

scholarly journals Design of a 1.9 GHz low-power LFSR Circuit using the Reed-Solomon Algorithm for Pseudo-Random Test Pattern Generation

2021 ◽  
Vol 13 (6) ◽  
Author(s):  
Vishnupriya Shivakumar ◽  
◽  
C. Senthilpari ◽  
Zubaida Yusoff ◽  
◽  
...  
Keyword(s):  
Power Consumption ◽  
Test Pattern ◽  
Pattern Generation ◽  
Maximum Length ◽  
Linear Feedback ◽  
Test Pattern Generation ◽  
Ic Design ◽  
Test Power ◽  
Random Test ◽  
Lower Test

A linear feedback shift register (LFSR) has been frequently used in the Built-in Self-Test (BIST) designs for the pseudo-random test pattern generation. The higher volume of the test patterns and the lower test power consumption are the key features in the large complex designs. The motivation of this study is to generate efficient pseudo-random test patterns by the proposed LFSR and to be applied in the BIST designs. For the BIST designs, the proposed LFSR satisfied with the main strategies such as re-seeding and lesser test power consumption. However, the reseeding approach was utilized by the maximum-length pseudo-random test patterns. The objective of this paper is to propose a new LFSR circuit based on the proposed Reed-Solomon (RS) algorithm. The RS algorithm is created by considering the factors of the maximum length test patterns with a minimum distance over the time t. Also, it has been achieved an effective generation of test patterns over a stage of complexity order O (m log2 m), where m denotes the total number of message bits. We analysed our RS LFSR mathematically using the feedback polynomial function to decrease the area overhead occupied in the designs. The simulation works of the proposed RS LFSR bit-wise stages are simulated using the TSMC 130 nm on the Mentor Graphics IC design platform. Experimental results showed that the proposed LFSR achieved the effective pseudo-random test patterns with a lower test power consumption of 25.13 µW and 49.9 µs. In addition, proposed LFSR along with existing authors’ LFSR are applied in the BIST design to examine their power consumption. Ultimately, overall simulations operated with the highest operating frequency environment as 1.9 GHz.

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