scholarly journals Calibration for Sample-And-Hold Mismatches in M-Channel TIADCs Based on Statistics

2019 ◽  
Vol 9 (1) ◽  
pp. 198 ◽  
Author(s):  
Xiangyu Liu ◽  
Hui Xu ◽  
Yinan Wang ◽  
Yingqiang Dai ◽  
Nan Li ◽  
...  
Keyword(s):  
Dynamic Performance ◽  
Sampling Rate ◽  
Analog To Digital ◽  
Sample And Hold ◽  
High Sampling Rate ◽  
Calibration Methods ◽  
Input Signals ◽  
Calibration Algorithm ◽  
Signal Simulation ◽  
Time Interleaved

Time-interleaved analog-to-digital converter (TIADC) is a good option for high sampling rate applications. However, the inevitable sample-and-hold (S/H) mismatches between channels incur undesirable error and then affect the TIADC’s dynamic performance. Several calibration methods have been proposed for S/H mismatches which either need training signals or have less extensive applicability for different input signals and different numbers of channels. This paper proposes a statistics-based calibration algorithm for S/H mismatches in M-channel TIADCs. Initially, the mismatch coefficients are identified by eliminating the statistical differences between channels. Subsequently, the mismatch-induced error is approximated by employing variable multipliers and differentiators in several Richardson iterations. Finally, the error is subtracted from the original output signal to approximate the expected signal. Simulation results illustrate the effectiveness of the proposed method, the selection of key parameters and the advantage to other methods.

scholarly journals Automatic Calibration Method of Channel Mismatches for Wideband TI-ADC System

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 56 ◽  
Author(s):  
Jingyu Li ◽  
Jiameng Pan ◽  
Yue Zhang
Keyword(s):  
Dynamic Range ◽  
Dynamic Performance ◽  
Sampling Rate ◽  
Calibration Method ◽  
Perfect Reconstruction ◽  
Automatic Calibration ◽  
Sampling System ◽  
Analog To Digital ◽  
Large Bandwidth ◽  
Time Interleaved

Time-interleaved analog-to-digital converter (TI-ADC) technology can increase the sampling rate without changing resolution. But, the dynamic performance of TI-ADC system is seriously deteriorated by channel mismatches. Under the condition of large bandwidth, gain mismatch and timing mismatch vary with the frequency, which cannot be regarded as fixed values. To improve the dynamic performance of the TI-ADC system, an automatic calibration method of channel mismatches for wideband TI-ADC system is proposed in this article. Frequency-dependent channel mismatches are estimated by the algorithm based on sine fitting, and compensated by the means based on perfect reconstruction. The entire sampling and calculation process is automated and tedious operation is simplified. A 6.8-GS/s 12-bit wideband TI-ADC system is implemented. This sampling system can achieve SNDR (signal-to-noise and distortion ratio) above 49 dB and SFDR (spurious-free dynamic range) above 57 dB for an input signal from 100 MHz to 3300 MHz. The proposed calibration method improves the SNDR over 10 dB and the SFDR over 15 dB. The dynamic performance of the sampling system is close to that of its sub-ADC.

A Bandwidth Mismatch Optimization Technique in Time-Interleaved Analog-to-Digital Converters

2019 ◽  
Vol 28 (06) ◽  
pp. 1950090
Author(s):  
Jian Luo ◽  
Jing Li ◽  
Shuangyi Wu ◽  
Ning Ning ◽  
Yang Liu
Keyword(s):  
Simulated Annealing Algorithm ◽  
Dynamic Range ◽  
Optimization Technique ◽  
Analog To Digital Converters ◽  
Analog To Digital ◽  
Limited Bandwidth ◽  
Behavior Simulation ◽  
Calibration Methods ◽  
Time Interleaved ◽  
Sampling Sequences

In time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches, caused by the limited bandwidth of input signal traces and sample circuits, seriously deteriorate the spurious-free dynamic range (SFDR) of the system. This paper analyzes the influence of bandwidth mismatch errors under different sampling sequences. Eventually, based on a randomization technique and the simulated annealing algorithm (SAA), a bandwidth mismatch optimization technique is presented that can work well with other bandwidth mismatch calibration methods. The behavior simulation results indicate that an improvement of 7[Formula: see text]dB in the SFDR can be achieved with this technique in a 16-channel TI-ADC after timing and gain calibration.

An Encoder Used in an Ultra High-Speed Folding and Interpolating ADC

2014 ◽  
Vol 1049-1050 ◽  
pp. 687-690
Author(s):  
Yu Han Gao ◽  
Ru Zhang Li ◽  
Dong Bing Fu ◽  
Yong Lu Wang ◽  
Zheng Ping Zhang
Keyword(s):  
High Speed ◽  
Binary Code ◽  
Sampling Rate ◽  
Gray Code ◽  
Cmos Technology ◽  
Careful Consideration ◽  
Analog To Digital ◽  
Interleaved Adc ◽  
Time Interleaved ◽  
Error Suppression

High speed encoder is the key element of high speed analog-to-digital converter (ADC). Therefor the type of encoder, the type of code, bubble error suppression and bit synchronization must be taken into careful consideration especially for folding and interpolating ADC. To reduce the bubble error which may resulted from the circuit niose, comparator metastability and other interference, the output of quantizer is first encoded with gray code and then converted to binary code. This high speed encoder is verified in the whole time-interleaved ADC with 0.18 Bi-CMOS technology, the whole ADC can achieve a SNR of 45 dB at the sampling rate of 5GHz and input frequency of 495MHz, meanwhile a bit error rate (BER) of less than 10-16 is ensured by this design.

scholarly journals A Statistic-Based Calibration Method for TIADC System

2015 ◽  
Vol 2015 ◽  
pp. 1-9 ◽  
Author(s):  
Kuojun Yang ◽  
Shulin Tian ◽  
Peng Ye ◽  
Peng Zhang ◽  
Yuanjin Zheng
Keyword(s):  
Sampling Rate ◽  
Calibration Method ◽  
Wide Frequency Range ◽  
Accurate Estimation ◽  
Analog To Digital ◽  
Average Value ◽  
Gain Error ◽  
Sampling Points ◽  
Interleaved Adc ◽  
Time Interleaved

Time-interleaved technique is widely used to increase the sampling rate of analog-to-digital converter (ADC). However, the channel mismatches degrade the performance of time-interleaved ADC (TIADC). Therefore, a statistic-based calibration method for TIADC is proposed in this paper. The average value of sampling points is utilized to calculate offset error, and the summation of sampling points is used to calculate gain error. After offset and gain error are obtained, they are calibrated by offset and gain adjustment elements in ADC. Timing skew is calibrated by an iterative method. The product of sampling points of two adjacent subchannels is used as a metric for calibration. The proposed method is employed to calibrate mismatches in a four-channel 5 GS/s TIADC system. Simulation results show that the proposed method can estimate mismatches accurately in a wide frequency range. It is also proved that an accurate estimation can be obtained even if the signal noise ratio (SNR) of input signal is 20 dB. Furthermore, the results obtained from a real four-channel 5 GS/s TIADC system demonstrate the effectiveness of the proposed method. We can see that the spectra spurs due to mismatches have been effectively eliminated after calibration.

An Effective CS-BP Algorithm for 2-D DOA Estimation

2011 ◽  
Vol 128-129 ◽  
pp. 62-65
Author(s):  
Yu Yan An ◽  
Sen Sen Bai
Keyword(s):  
Frequency Modulation ◽  
Sampling Rate ◽  
Doa Estimation ◽  
Bp Algorithm ◽  
Basis Pursuit ◽  
Two Dimensional ◽  
Digital Converter ◽  
Analog To Digital ◽  
High Sampling Rate ◽  
Simulation Results

The bandwidth of the direction of arrival (DOA) estimation requires high sampling rate which extends the current analog to digital converter capacity. The paper presents an effective basis pursuit (BP) algorithm based on compressive sensing (CS) signals, which is called CS-BP algorithm, for two-dimensional (2-D) DOA estimation of Linear Frequency Modulation (LFM ). The simulation results verified that the method can effectively reduce the sampling data, and improve DOA estimation performance and efficiency.

scholarly journals Synchronous Mixing Architecture for Digital Bandwidth Interleaving Sampling System

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1998
Author(s):  
Xiaochang Jiang ◽  
Jie Wu ◽  
Yubo Ma
Keyword(s):  
High Frequency ◽  
Dynamic Range ◽  
Sampling Rate ◽  
Poor Performance ◽  
Sampling System ◽  
Analog To Digital ◽  
Frequency Components ◽  
Time Interleaved ◽  
Evaluation Platform ◽  
Hybrid Filter Bank

By using a mixer to down-convert the high frequency components of a signal, digital bandwidth interleaving (DBI) technology can simultaneously increase the sampling rate and bandwidth of the sampling system, compared to the time-interleaved and hybrid filter bank. However, the software and hardware of the classical architecture are too complicated, which also leads to poor performance. In particular, the pilot tone used to synchronize the analog and digital local oscillators (LO) of mixers intermodulates with the high frequency components of the signal, resulting in larger spurs. This paper proposes a synchronous mixing architecture for the DBI system, where the LO of the analog mixer is synchronized with the sampling clock of the analog-to-digital converter. Its hardware and software are simplified—the pilot tone used to synchronize the LOs can also be removed. An evaluation platform with a sampling rate of 250 MSPS is implemented to illustrate the performance of the new architecture. The result shows that the spurious free dynamic range (SFDR) of the new architecture is more than 20 dB higher than the classical one in a high frequency range. The rise time of a step signal of the new architecture is 0.578 ± 0.070 ns faster than the classical one with the same bandwidth (90 MHz).

Noise-Coupled Time-Interleaved Delta–Sigma Modulator with Reduced Hardware Complexity

2020 ◽  
pp. 2150071
Author(s):  
Mahmud Abdoli ◽  
Esmaeil Najafi Aghdam
Keyword(s):  
High Speed ◽  
Sampling Rate ◽  
Hardware Complexity ◽  
Analog To Digital ◽  
Noise Transfer Function ◽  
Delta Sigma Modulator ◽  
Novel Structure ◽  
Delta Sigma ◽  
Time Interleaved ◽  
Better Than

Developing an analog-to-digital converter (ADC) based on the time-interleaved delta–sigma modulator (TIDSM) is an appropriate technique to attain high-speed ADCs. TIDSMs can be successfully accomplished with the aid of developing the block digital filtering (BDF) method. In this approach, [Formula: see text] mutually cross-connection delta–sigma modulators are used, whereby each one of them operates at a sampling rate of [Formula: see text], leading to an effective sampling rate of [Formula: see text]. In this study, a novel structure is proposed based on the Noise Coupled time-interleaved delta–sigma modulator (NC-TIDSM) with reduced hardware complexity. This structure not only increases the overall noise transfer function (NTF) order, but also reduces the hardware element counts. The simulation results demonstrate that the SNDRs of the first-order two-channel and four-channel NC-TIDSM with reduced hardware are 13 and 15 dB better than those of their BDF technique counterparts; also, the SNDR of the second-order two-channel NC-TIDSM with reduced hardware is 8 dB better than that of their BDF technique counterpart; also, the hardware element quantities are reduced dramatically. Moreover, some practical challenges such as the finite op-amp’s gain and mismatching effects that directly affect the circuit implementation of the proposed structure have been described. Furthermore, the hardware complexity of the proposed structures is reduced considerably in comparison to that of the BDF technique with the NC-TIDSM structure.

scholarly journals A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS

Electronics ◽  
2019 ◽  
Vol 9 (1) ◽  
pp. 20
Author(s):  
Hao Ding ◽  
Danyu Wu ◽  
Xuqiang Zheng ◽  
Lei Zhou ◽  
Teng Chen ◽  
...  
Keyword(s):  
High Speed ◽  
Sampling Rate ◽  
Harmonic Distortion ◽  
Large Area ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Sample And Hold ◽  
Sige Bicmos ◽  
The Common ◽  
Time Interleaved

This paper presents a 20 GS/s four-channel time-interleaved sample-and-hold amplifier (SHA), which aims to improve the harmonic distortion performance, eliminate the common-mode voltage fall in track-to-hold transition, and solve the difficulty of timing mismatch calibration among different sampling channels. In data path, the harmonic distortion of the track-hold switch is optimized by introducing a distortion-improving resistor into the switched emitter follower. The common-mode voltage fall is eliminated by an inserted delay-regulating resistor. Additionally, broadband data buffers are utilized to further guarantee a wide bandwidth. In clock path, an interpolator-based phase regulator in analog domain is implemented to calibrate the timing mismatch, hence avoiding the large area cost and complicated algorithm in the digital domain. Fabricated in a 0.18 μm SiGe BiCMOS process, the experimental results show that the SHA achieves a bandwidth of 16 GHz and a total harmonic distortion of −39.6 to approximately −51.8 dB with a −3 dBm input. By applying the proposed sampling phase regulator, the timing mismatch can be optimized to satisfy the requirement of 6-bit resolution at a 4 × 5 GS/s sampling rate. The proposed SHA shows prominent performance on both bandwidth and linearity, which makes it suitable for ultra-high-speed communication networks.

scholarly journals Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2545
Author(s):  
Kihyun Kim ◽  
Sein Oh ◽  
Hyungil Chae
Keyword(s):  
High Speed ◽  
Sampling Rate ◽  
Cmos Process ◽  
Noise Shaping ◽  
Mismatch Error ◽  
Analog To Digital ◽  
Current Sharing ◽  
High Sampling Rate ◽  
Good Energy ◽  
Two Phases

A 2-then-1-bit/cycle noise-shaping successive-approximation register (SAR) analog-to-digital converter (ADC) for high sampling rate and high resolution is presented. The conversion consists of two phases of a coarse 2-bit/cycle SAR conversion for high speed and a fine 1-bit/cycle noise-shaping SAR conversion for high accuracy. The coarse conversion is performed by both voltage and time comparison for low power consumption. A redundancy after the coarse conversion corrects the error caused by a jitter noise during the time comparison. Additionally, a mismatch error between signal and reference paths is eliminated with the help of a tail-current-sharing comparator. The proposed ADC was designed in a 28 nm CMOS process, and the simulation result shows a 68.2 dB signal-to-noise distortion (SNDR) for a sampling rate of 480 MS/s and a bandwidth of 60 MHz with good energy efficiency.

A 10-GS/s 6-Bit Track-and-Hold Amplifier for Time-Interleaved SAR ADCs in 65-nm CMOS

2016 ◽  
Vol 25 (08) ◽  
pp. 1650084 ◽  
Author(s):  
Liang Zhang ◽  
Dengquan Li ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
Input Signal ◽  
Sampling Rate ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Common Source ◽  
Digital Converter ◽  
Input Buffer ◽  
Analog To Digital ◽  
Source Follower ◽  
Time Interleaved

This paper presents a 10-GS/s 6-bit track-and-hold amplifier (THA), which is designed for a 16-way time-interleaved successive approximation register (SAR) analog to digital converter (ADC). To extend the bandwidth, a differential source-degenerated common-source amplifier with peaking inductance is adopted as an input buffer. A switched source follower master track-and-hold stage samples the 800-mVPP differential input signal at 10[Formula: see text]GHz. Moreover, the THA cancels the feed-through in hold mode by a clock-controlled transistor. The proposed THA is simulated in 65-nm CMOS technology. It operates with 1.8/1.2-V supply and consumes 84.8[Formula: see text]mW. At a sampling rate of 10[Formula: see text]GS/s, [Formula: see text]41-dB total harmonic distortion (THD) is achieved with input frequencies up to 5[Formula: see text]GHz.

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