Accurate Direction-of-Arrival Estimation Method based on Space-Time Modulated Metasurface

In this paper, we present a metasurface-based Direction of Arrival (DoA) estimation method that exploits the properties of space-time modulated reflecting metasurfaces to estimate in real-time the impinging angle of an illuminating monochromatic plane wave. The approach makes use of the amplitude unbalance of the received fields at broadside at the frequencies of the two first-order harmonics generated by the interaction between the incident plane wave and the modulated metasurface. Here, we first describe analytically how to generate the desired higher-order harmonics in the reflected spectrum and how to realize the breaking of the spatial symmetry of each order harmonic scattering pattern. Then, the one dimensional (1D) omnidirectional incident angle can be analytically computed using +1st and -1st order harmonics. The approach is also extended to 2D DoA estimation by using two orthogonally arranged 1D DoA modulation arrays. The accuracy of 1D DoA estimation is verified through full-wave numerical simulations. Compared to conventional DoA estimation methods, the proposed approach simplifies the computation and hardware complexity, ensuring at the same time estimation accuracy. The proposed method may have potential applications in wireless communications, target recognition, and identification.

Accurate Direction-of-Arrival Estimation Method based on Space-Time Modulated Metasurface

In this paper, we present a metasurface-based Direction of Arrival (DoA) estimation method that exploits the properties of space-time modulated reflecting metasurfaces to estimate in real-time the impinging angle of an illuminating monochromatic plane wave. The approach makes use of the amplitude unbalance of the received fields at broadside at the frequencies of the two first-order harmonics generated by the interaction between the incident plane wave and the modulated metasurface. Here, we first describe analytically how to generate the desired higher-order harmonics in the reflected spectrum and how to realize the breaking of the spatial symmetry of each order harmonic scattering pattern. Then, the one dimensional (1D) omnidirectional incident angle can be analytically computed using +1st and -1st order harmonics. The approach is also extended to 2D DoA estimation by using two orthogonally arranged 1D DoA modulation arrays. The accuracy of 1D DoA estimation is verified through full-wave numerical simulations. Compared to conventional DoA estimation methods, the proposed approach simplifies the computation and hardware complexity, ensuring at the same time estimation accuracy. The proposed method may have potential applications in wireless communications, target recognition, and identification.

A Novel, Low Computational Complexity, Parallel Swarm Algorithm for Application in Low-Energy Devices

In this work, we propose a novel metaheuristic algorithm that evolved from a conventional particle swarm optimization (PSO) algorithm for application in miniaturized devices and systems that require low energy consumption. The modifications allowed us to substantially reduce the computational complexity of the PSO algorithm, translating to reduced energy consumption in hardware implementation. This is a paramount feature in the devices used, for example, in wireless sensor networks (WSNs) or wireless body area sensors (WBANs), in which particular devices have limited access to a power source. Various swarm algorithms are widely used in solving problems that require searching for an optimal solution, with simultaneous occurrence of a different number of sub-optimal solutions. This makes the hardware implementation worthy of consideration. However, hardware implementation of the conventional PSO algorithm is challenging task. One of the issues is an efficient implementation of the randomization function. In this work, we propose novel methods to work around this problem. In the proposed approach, we replaced the block responsible for generating random values using deterministic methods, which differentiate the trajectories of particular particles in the swarm. Comprehensive investigations in the software model of the modified algorithm have shown that its performance is comparable with or even surpasses the conventional PSO algorithm in a multitude of scenarios. The proposed algorithm was tested with numerous fitness functions to verify its flexibility and adaptiveness to different problems. The paper also presents the hardware implementation of the selected blocks that modify the algorithm. In particular, we focused on reducing the hardware complexity, achieving high-speed operation, while reducing energy consumption.

Carrier-Assisted Phase Retrieval

Phase-retrieval (PR) schemes based on the modified Gerchberg-Saxton (GS) algorithm capture the full-field employing a dispersive element and intensity-only measurements to eliminate the use of a local oscillator. In this work, we propose two carrier-assisted PR schemes, namely central carrier-assisted PR (CCA-PR) and edge carrier-assisted PR (ECA-PR), to improve the comprehensive performance of PR receiver in terms of convergence speed, redundancy, and computational complexity. The proposed CCA-PR recovers the electrical field employing a reference carrier at 0 GHz with several iterations between two projection planes. It avoids pilot symbols and digital backpropagation to the transmitter and offers a flexible electrical bandwidth requirement compared with conventional PR schemes. To lower the carrier-to-signal power ratio (CSPR) requirement and enable faster convergence for the carrier-assisted PR schemes, the ECA-PR is proposed to obtain the initial phase for the GS algorithm. We numerically characterize the performance of the two schemes and experimentally demonstrate them for 30 GBaud 16-quadrature amplitude modulation (16-QAM) transmission over 80 km single-mode fiber with a bit error rate (BER) below the threshold of 7% hard-decision forward error correction (HD-FEC). Several critical parameters are analyzed, including the applied dispersion value, CSPR, and electrical bandwidth. Moreover, we compare the hardware complexity and optical signal-to-noise ratio (OSNR) sensitivity of proposed PR schemes with mainstream field recovery schemes.

Carrier-Assisted Phase Retrieval

Phase-retrieval (PR) schemes based on the modified Gerchberg-Saxton (GS) algorithm capture the full-field employing a dispersive element and intensity-only measurements to eliminate the use of a local oscillator. In this work, we propose two carrier-assisted PR schemes, namely central carrier-assisted PR (CCA-PR) and edge carrier-assisted PR (ECA-PR), to improve the comprehensive performance of PR receiver in terms of convergence speed, redundancy, and computational complexity. The proposed CCA-PR recovers the electrical field employing a reference carrier at 0 GHz with several iterations between two projection planes. It avoids pilot symbols and digital backpropagation to the transmitter and offers a flexible electrical bandwidth requirement compared with conventional PR schemes. To lower the carrier-to-signal power ratio (CSPR) requirement and enable faster convergence for the carrier-assisted PR schemes, the ECA-PR is proposed to obtain the initial phase for the GS algorithm. We numerically characterize the performance of the two schemes and experimentally demonstrate them for 30 GBaud 16-quadrature amplitude modulation (16-QAM) transmission over 80 km single-mode fiber with a bit error rate (BER) below the threshold of 7% hard-decision forward error correction (HD-FEC). Several critical parameters are analyzed, including the applied dispersion value, CSPR, and electrical bandwidth. Moreover, we compare the hardware complexity and optical signal-to-noise ratio (OSNR) sensitivity of proposed PR schemes with mainstream field recovery schemes.

Computing a Group of Polynomials over a Galois Field in FPGA Architecture

For the most extensive range of tasks, such as real-time data processing in intelligent transport systems, etc., advanced computer-based techniques are required. They include field-programmable gate arrays (FPGAs). This paper proposes a method of pre-calculating the hardware complexity of computing a group of polynomial functions depending on the number of input variables of the said functions, based on the microchips of FPGAs. These assessments are reduced for a group of polynomial functions due to computing the common values of elementary polynomials. Implementation is performed using similar software IP-cores adapted to the architecture of user-programmable logic arrays. The architecture of FPGAs includes lookup tables and D flip-flops. This circumstance ensures that the pipelined data processing provides the highest operating speed of a device, which implements the group of polynomial functions defined over a Galois field, independently of the number of variables of the said functions. A group of polynomial functions is computed based on common variables. Therefore, the input/output blocks of FPGAs are not a significant limiting factor for the hardware complexity estimates. Estimates obtained in using the method proposed allow evaluating the amount of the reconfigurable resources of FPGAs, required for implementing a group of polynomial functions defined over a Galois field. This refers to both the existing FPGAs and promising ones that have not yet been implemented.

Design of ACS Architecture Using FinFET and CNTFET Devices for Low-Power Viterbi Decoder Using Asynchronous Techniques for Digital Communication Systems

Viterbi algorithm is the most popular algorithm used to decode the convolution code, but its computational complexity increases exponentially with the increasing constraint length due to a large number of Trellis transitions. However, high constraint length is necessary to improve the accuracy of the decoding process for the high rate convolution code. In particular, the Add-Compare-Select (ACS) module of the Viterbi Decoder will have large numbers of trellis states and trellis transitions with increased constraint lengths, which give rise to high hardware complexity and large power consumption. As the performance of the Viterbi decoder mainly depends on its efficient implementation of the ACS module, in the literature, several methods are presented for the implementation of ACS for the Viterbi decoder. The methods based on Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer, Shannon’s decomposition circuits, body-biased pseudo-NMOS logic and Quasi Delay Insensitive (QDI) timing model performance is analyzed. The methods are implemented using CMOS technology. In this paper, FinFET and CNTFET-based ACS implementation is performed. From the analysis, it has been found that the Carbon Nanotube-based implementation is better in performance when compared to the CMOS and FinFET technology. The proposed QDI model and retiming circuits for ACS block operate above 1[Formula: see text]GHz with high driving current and low power.

Low complexity full duplex MIMO systems: Analog canceler architectures, beamforming design, and future directions

The hardware complexity of the analog Self-Interference (SI) canceler in conventional full duplex Multiple Input Multiple Output (MIMO) designs mostly scales with the number of transmit and receive antennas, thus exploiting the benefits of analog cancellation becomes impractical for full duplex MIMO transceivers, even for a moderate number of antennas. In this paper, we provide an overview of two recent hardware architectures for the analog canceler comprising of reduced number of cancellation elements, compared to the state of the art, and simple multiplexers for efficient signal routing among the transceiver radio-frequency chains. The one architecture is based on analog taps and the other on AUXiliary (AUX) Transmitters (TXs). In contrast to the available analog cancellation architectures, the values for each tap or each AUX TX and the configuration of the multiplexers are jointly designed with the digital transceiver beamforming filters according to desired performance objectives. We present a general optimization framework for the joint design of analog SI cancellation and digital beamforming, and detail an example algorithmic solution for the sum-rate optimization objective. Our representative computer simulation results demonstrate the superiority, both in terms of hardware complexity and achievable performance, of the presented low complexity full duplex MIMO schemes over the relative available ones in the literature. We conclude the paper with a discussion on recent simultaneous transmit and receive operations capitalizing on the presented architectures, and provide a list of open challenges and research directions for future FD MIMO communication systems, as well as their promising applications.