scholarly journals Automatic Calibration Method of Channel Mismatches for Wideband TI-ADC System

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 56 ◽  
Author(s):  
Jingyu Li ◽  
Jiameng Pan ◽  
Yue Zhang
Keyword(s):  
Dynamic Range ◽  
Dynamic Performance ◽  
Sampling Rate ◽  
Calibration Method ◽  
Perfect Reconstruction ◽  
Automatic Calibration ◽  
Sampling System ◽  
Analog To Digital ◽  
Large Bandwidth ◽  
Time Interleaved

Time-interleaved analog-to-digital converter (TI-ADC) technology can increase the sampling rate without changing resolution. But, the dynamic performance of TI-ADC system is seriously deteriorated by channel mismatches. Under the condition of large bandwidth, gain mismatch and timing mismatch vary with the frequency, which cannot be regarded as fixed values. To improve the dynamic performance of the TI-ADC system, an automatic calibration method of channel mismatches for wideband TI-ADC system is proposed in this article. Frequency-dependent channel mismatches are estimated by the algorithm based on sine fitting, and compensated by the means based on perfect reconstruction. The entire sampling and calculation process is automated and tedious operation is simplified. A 6.8-GS/s 12-bit wideband TI-ADC system is implemented. This sampling system can achieve SNDR (signal-to-noise and distortion ratio) above 49 dB and SFDR (spurious-free dynamic range) above 57 dB for an input signal from 100 MHz to 3300 MHz. The proposed calibration method improves the SNDR over 10 dB and the SFDR over 15 dB. The dynamic performance of the sampling system is close to that of its sub-ADC.

scholarly journals Synchronous Mixing Architecture for Digital Bandwidth Interleaving Sampling System

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1998
Author(s):  
Xiaochang Jiang ◽  
Jie Wu ◽  
Yubo Ma
Keyword(s):  
High Frequency ◽  
Dynamic Range ◽  
Sampling Rate ◽  
Poor Performance ◽  
Sampling System ◽  
Analog To Digital ◽  
Frequency Components ◽  
Time Interleaved ◽  
Evaluation Platform ◽  
Hybrid Filter Bank

By using a mixer to down-convert the high frequency components of a signal, digital bandwidth interleaving (DBI) technology can simultaneously increase the sampling rate and bandwidth of the sampling system, compared to the time-interleaved and hybrid filter bank. However, the software and hardware of the classical architecture are too complicated, which also leads to poor performance. In particular, the pilot tone used to synchronize the analog and digital local oscillators (LO) of mixers intermodulates with the high frequency components of the signal, resulting in larger spurs. This paper proposes a synchronous mixing architecture for the DBI system, where the LO of the analog mixer is synchronized with the sampling clock of the analog-to-digital converter. Its hardware and software are simplified—the pilot tone used to synchronize the LOs can also be removed. An evaluation platform with a sampling rate of 250 MSPS is implemented to illustrate the performance of the new architecture. The result shows that the spurious free dynamic range (SFDR) of the new architecture is more than 20 dB higher than the classical one in a high frequency range. The rise time of a step signal of the new architecture is 0.578 ± 0.070 ns faster than the classical one with the same bandwidth (90 MHz).

scholarly journals A Statistic-Based Calibration Method for TIADC System

2015 ◽  
Vol 2015 ◽  
pp. 1-9 ◽  
Author(s):  
Kuojun Yang ◽  
Shulin Tian ◽  
Peng Ye ◽  
Peng Zhang ◽  
Yuanjin Zheng
Keyword(s):  
Sampling Rate ◽  
Calibration Method ◽  
Wide Frequency Range ◽  
Accurate Estimation ◽  
Analog To Digital ◽  
Average Value ◽  
Gain Error ◽  
Sampling Points ◽  
Interleaved Adc ◽  
Time Interleaved

Time-interleaved technique is widely used to increase the sampling rate of analog-to-digital converter (ADC). However, the channel mismatches degrade the performance of time-interleaved ADC (TIADC). Therefore, a statistic-based calibration method for TIADC is proposed in this paper. The average value of sampling points is utilized to calculate offset error, and the summation of sampling points is used to calculate gain error. After offset and gain error are obtained, they are calibrated by offset and gain adjustment elements in ADC. Timing skew is calibrated by an iterative method. The product of sampling points of two adjacent subchannels is used as a metric for calibration. The proposed method is employed to calibrate mismatches in a four-channel 5 GS/s TIADC system. Simulation results show that the proposed method can estimate mismatches accurately in a wide frequency range. It is also proved that an accurate estimation can be obtained even if the signal noise ratio (SNR) of input signal is 20 dB. Furthermore, the results obtained from a real four-channel 5 GS/s TIADC system demonstrate the effectiveness of the proposed method. We can see that the spectra spurs due to mismatches have been effectively eliminated after calibration.

NEW SAMPLING METHOD TO IMPROVE THE SFDR OF WIDE BANDWIDTH ADC DEDICATED TO NEXT GENERATION WIRELESS TRANSCEIVER

2004 ◽  
Vol 13 (06) ◽  
pp. 1183-1201
Author(s):  
KAMAL EL-SANKARY ◽  
ALI ASSI ◽  
MOHAMAD SAWAN
Keyword(s):  
High Speed ◽  
Sampling Method ◽  
Dynamic Range ◽  
Sampling Rate ◽  
Analog To Digital ◽  
Wireless Transceiver ◽  
Spurious Free Dynamic Range ◽  
Interleaved Adc ◽  
Time Interleaved ◽  
Free Dynamic

Modern wireless communication standards that support high rates of voice and video streaming need high-speed Analog-to-Digital Converters (ADCs) with wide Spurious-Free Dynamic Range (SFDR). Conventional time-interleaved ADCs suffer from spurious components that seriously affect the SFDR. In this paper, we present the mathematical background describing the effect of randomizing the samples among the interleaved ADCs and we propose a digitally oriented method based on this analysis to randomize the mismatches among the ADC channels. Analyses and simulations show the effectiveness of the proposed approach in multi-channel ADCs with arbitrary bit resolution, channel's number and sampling rate. For a 10-bit 500 MS/s ADC, the SFDR achieved using the proposed randomizing method can be as wide as 75 dB, which is an enhancement of more than 26 dB comparing to the conventional time interleaved ADC.

scholarly journals Calibration for Sample-And-Hold Mismatches in M-Channel TIADCs Based on Statistics

2019 ◽  
Vol 9 (1) ◽  
pp. 198 ◽  
Author(s):  
Xiangyu Liu ◽  
Hui Xu ◽  
Yinan Wang ◽  
Yingqiang Dai ◽  
Nan Li ◽  
...  
Keyword(s):  
Dynamic Performance ◽  
Sampling Rate ◽  
Analog To Digital ◽  
Sample And Hold ◽  
High Sampling Rate ◽  
Calibration Methods ◽  
Input Signals ◽  
Calibration Algorithm ◽  
Signal Simulation ◽  
Time Interleaved

Time-interleaved analog-to-digital converter (TIADC) is a good option for high sampling rate applications. However, the inevitable sample-and-hold (S/H) mismatches between channels incur undesirable error and then affect the TIADC’s dynamic performance. Several calibration methods have been proposed for S/H mismatches which either need training signals or have less extensive applicability for different input signals and different numbers of channels. This paper proposes a statistics-based calibration algorithm for S/H mismatches in M-channel TIADCs. Initially, the mismatch coefficients are identified by eliminating the statistical differences between channels. Subsequently, the mismatch-induced error is approximated by employing variable multipliers and differentiators in several Richardson iterations. Finally, the error is subtracted from the original output signal to approximate the expected signal. Simulation results illustrate the effectiveness of the proposed method, the selection of key parameters and the advantage to other methods.

A Bandwidth Mismatch Optimization Technique in Time-Interleaved Analog-to-Digital Converters

2019 ◽  
Vol 28 (06) ◽  
pp. 1950090
Author(s):  
Jian Luo ◽  
Jing Li ◽  
Shuangyi Wu ◽  
Ning Ning ◽  
Yang Liu
Keyword(s):  
Simulated Annealing Algorithm ◽  
Dynamic Range ◽  
Optimization Technique ◽  
Analog To Digital Converters ◽  
Analog To Digital ◽  
Limited Bandwidth ◽  
Behavior Simulation ◽  
Calibration Methods ◽  
Time Interleaved ◽  
Sampling Sequences

In time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches, caused by the limited bandwidth of input signal traces and sample circuits, seriously deteriorate the spurious-free dynamic range (SFDR) of the system. This paper analyzes the influence of bandwidth mismatch errors under different sampling sequences. Eventually, based on a randomization technique and the simulated annealing algorithm (SAA), a bandwidth mismatch optimization technique is presented that can work well with other bandwidth mismatch calibration methods. The behavior simulation results indicate that an improvement of 7[Formula: see text]dB in the SFDR can be achieved with this technique in a 16-channel TI-ADC after timing and gain calibration.

scholarly journals A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1551 ◽  
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Capacitor Mismatch ◽  
Gain Error ◽  
Spurious Free Dynamic Range ◽  
Time Interleaved ◽  
Free Dynamic

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

An Encoder Used in an Ultra High-Speed Folding and Interpolating ADC

2014 ◽  
Vol 1049-1050 ◽  
pp. 687-690
Author(s):  
Yu Han Gao ◽  
Ru Zhang Li ◽  
Dong Bing Fu ◽  
Yong Lu Wang ◽  
Zheng Ping Zhang
Keyword(s):  
High Speed ◽  
Binary Code ◽  
Sampling Rate ◽  
Gray Code ◽  
Cmos Technology ◽  
Careful Consideration ◽  
Analog To Digital ◽  
Interleaved Adc ◽  
Time Interleaved ◽  
Error Suppression

High speed encoder is the key element of high speed analog-to-digital converter (ADC). Therefor the type of encoder, the type of code, bubble error suppression and bit synchronization must be taken into careful consideration especially for folding and interpolating ADC. To reduce the bubble error which may resulted from the circuit niose, comparator metastability and other interference, the output of quantizer is first encoded with gray code and then converted to binary code. This high speed encoder is verified in the whole time-interleaved ADC with 0.18 Bi-CMOS technology, the whole ADC can achieve a SNR of 45 dB at the sampling rate of 5GHz and input frequency of 495MHz, meanwhile a bit error rate (BER) of less than 10-16 is ensured by this design.

scholarly journals A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (2) ◽  
pp. 253
Author(s):  
Dong Wang ◽  
Jian Luan ◽  
Xuan Guo ◽  
Lei Zhou ◽  
Danyu Wu ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Dynamic Performance ◽  
Open Loop ◽  
Total Power ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Self Calibration ◽  
Differential Nonlinearity ◽  
Bicmos Technology ◽  
Sige Bicmos

A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 μm SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 × 3.6 mm2, consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.

Area-Efficient Capacitor-Splitting Switching Scheme with a Nearly Constant Common-Mode Voltage for SAR ADCs

2019 ◽  
Vol 29 (10) ◽  
pp. 2020005
Author(s):  
Hao Wang ◽  
Wenming Xie ◽  
Zhixin Chen
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Switching Scheme ◽  
Common Mode ◽  
Analog To Digital ◽  
Common Mode Voltage ◽  
Switching Method ◽  
Area Efficient

A novel area-efficient switching scheme is proposed for the successive approximation register (SAR) analog-to-digital converters (ADCs). The capacitor-splitting structure, charge-average switching technique, and [Formula: see text] (equal to [Formula: see text]/4) are combined together and optimized to realize the proposed switching scheme. [Formula: see text] is only used in the last two bit cycles, which affects the ADC accuracy little and reduces capacitor area by half. It achieves a 98% less switching energy and an 87.5% less capacitor area compared with the conventional switching method. In addition, the DAC output common-mode voltage is approximately constant. Thus, the proposed switching method is a good tradeoff among power consumption, capacitor area, DAC output common-mode voltage, and ADC accuracy. The proposed SAR ADC is simulated in 0.18[Formula: see text][Formula: see text]m CMOS technology with a supply voltage of 0.6[Formula: see text]V and at a sampling rate of 20[Formula: see text]kS/s. The signal-to-noise-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 58.2 and 73.7[Formula: see text]dB, respectively. The effective number of bits (ENOB) is 9.4. It consumes 42[Formula: see text]nW, resulting in a figure-of-merit (FoM) of 3.11 fJ/conversion-step.

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