scholarly journals A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS

Electronics ◽  
2019 ◽  
Vol 9 (1) ◽  
pp. 20
Author(s):  
Hao Ding ◽  
Danyu Wu ◽  
Xuqiang Zheng ◽  
Lei Zhou ◽  
Teng Chen ◽  
...  
Keyword(s):  
High Speed ◽  
Sampling Rate ◽  
Harmonic Distortion ◽  
Large Area ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Sample And Hold ◽  
Sige Bicmos ◽  
The Common ◽  
Time Interleaved

This paper presents a 20 GS/s four-channel time-interleaved sample-and-hold amplifier (SHA), which aims to improve the harmonic distortion performance, eliminate the common-mode voltage fall in track-to-hold transition, and solve the difficulty of timing mismatch calibration among different sampling channels. In data path, the harmonic distortion of the track-hold switch is optimized by introducing a distortion-improving resistor into the switched emitter follower. The common-mode voltage fall is eliminated by an inserted delay-regulating resistor. Additionally, broadband data buffers are utilized to further guarantee a wide bandwidth. In clock path, an interpolator-based phase regulator in analog domain is implemented to calibrate the timing mismatch, hence avoiding the large area cost and complicated algorithm in the digital domain. Fabricated in a 0.18 μm SiGe BiCMOS process, the experimental results show that the SHA achieves a bandwidth of 16 GHz and a total harmonic distortion of −39.6 to approximately −51.8 dB with a −3 dBm input. By applying the proposed sampling phase regulator, the timing mismatch can be optimized to satisfy the requirement of 6-bit resolution at a 4 × 5 GS/s sampling rate. The proposed SHA shows prominent performance on both bandwidth and linearity, which makes it suitable for ultra-high-speed communication networks.

scholarly journals A New Approach to the PWM Modulation for the Multiphase Matrix Converters Supplying Loads with Open-End Winding

Energies ◽  
2021 ◽  
Vol 14 (2) ◽  
pp. 466
Author(s):  
Pawel Szczepankowski ◽  
Natalia Strzelecka ◽  
Enrique Romero-Cadaval
Keyword(s):  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Simulation Software ◽  
Common Mode ◽  
New Approach ◽  
Matrix Converters ◽  
Load Voltage ◽  
Common Mode Voltage ◽  
The Common ◽  
Open End Winding

This article presents three variants of the Pulse Width Modulation (PWM) for the Double Square Multiphase type Conventional Matrix Converters (DSM-CMC) supplying loads with the open-end winding. The first variant of PWM offers the ability to obtain zero value of the common-mode voltage at the load’s terminals and applies only six switches within the modulation period. The second proposal archives for less Total Harmonic Distortion (THD) of the generated load voltage. The third variant of modulation concerns maximizing the voltage transfer ratio, minimizing the number of switching, and the common-mode voltage cancellation. The discussed modulations are based on the concept of sinusoidal voltage quadrature signals, which can be an effective alternative to the classic space-vector approach. In the proposed approach, the geometrical arrangement of basic vectors needed to synthesize output voltages is built from the less number of vectors, which is equal to the number of the matrix converter’s terminals. The PWM duty cycle computation is performed using only a second-order determinant of the voltages coordinate matrix without using trigonometric functions. A new approach to the PWM duty cycles computing and the load voltage synthesis by 5 × 5 and 12 × 12 topologies has been verified using the PSIM simulation software.

scholarly journals A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 350 ◽  
Author(s):  
Xu Bai ◽  
Jianzhong Zhao ◽  
Shi Zuo ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Common Mode ◽  
Serial Interface ◽  
Common Mode Voltage ◽  
Rail To Rail ◽  
The Common ◽  
28 Nm

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 [email protected] Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.

scholarly journals Carrier-Based Common Mode Voltage Control Techniques in Three-Level Diode-Clamped Inverter

2012 ◽  
Vol 2012 ◽  
pp. 1-12 ◽  
Author(s):  
Pradyumn Chaturvedi ◽  
Shailendra Jain ◽  
Pramod Agarwal
Keyword(s):  
Output Voltage ◽  
Harmonic Distortion ◽  
Comparison Method ◽  
Rate Of Change ◽  
Common Mode ◽  
Multilevel Inverters ◽  
Common Mode Voltage ◽  
Voltage Signal ◽  
Comparable Performance ◽  
The Common

Switching converters are used in electric drive applications to produce variable voltage, variable frequency supply which generates harmful large dv/dt and high-frequency common mode voltages (CMV). Multilevel inverters generate lower CMV as compared to conventional two-level inverters. This paper presents simple carrier-based technique to control the common mode voltages in multilevel inverters using different structures of sine-triangle comparison method such as phase disposition (PD), phase opposition disposition (POD) by adding common mode voltage offset signal to actual reference voltage signal. This paper also presented the method to optimize the magnitude of this offset signal to reduce CMV and total harmonic distortion in inverter output voltage. The presented techniques give comparable performance as obtained in complex space vector-based control strategy, in terms of number of commutations, magnitude, and rate of change of CMV and harmonic profile of inverter output voltage. Simulation and experimental results presented confirm the effectiveness of the proposed techniques to control the common mode voltages.

scholarly journals Leakage Current Reduction in Single-Phase Grid-Connected Inverters—A Review

2020 ◽  
Vol 10 (7) ◽  
pp. 2384 ◽  
Author(s):  
Adyr A. Estévez-Bén ◽  
Alfredo Alvarez-Diazcomas ◽  
Gonzalo Macias-Bobadilla ◽  
Juvenal Rodríguez-Reséndiz
Keyword(s):  
Leakage Current ◽  
Harmonic Distortion ◽  
Clean Energy ◽  
Photovoltaic Module ◽  
Common Mode ◽  
Advantages And Disadvantages ◽  
Common Mode Voltage ◽  
The Common ◽  
Ac Converters ◽  
Current Reduction

The rise in renewable energy has increased the use of DC/AC converters, which transform the direct current to alternating current. These devices, generally called inverters, are mainly used as an interface between clean energy and the grid. It is estimated that 21% of the global electricity generation capacity from renewable sources is supplied by photovoltaic systems. In these systems, a transformer to ensure grid isolation is used. Nevertheless, the transformer makes the system expensive, heavy, bulky and reduces its efficiency. Therefore, transformerless schemes are used to eliminate the mentioned disadvantages. One of the main drawbacks of transformerless topologies is the presence of a leakage current between the physical earth of the grid and the parasitic capacitances of the photovoltaic module terminals. The leakage current depends on the value of the parasitic capacitances of the panel and the common-mode voltage. At the same time, the common-mode voltage depends on the modulation strategy used. Therefore, by the manipulation of the modulation technique, is accomplished a decrease in the leakage current. However, the connection standards for photovoltaic inverters establish a maximum total harmonic distortion of 5%. In this paper an analysis of the common-mode voltage and its influence on the value of the leakage current is described. The main topologies and strategies used to reduce the leakage current in transformerless schemes are summarized, highlighting advantages and disadvantages and establishing points of comparison with similar topologies. A comparative table with the most important aspects of each converter is shown based on number of components, modes of operation, type of modulation strategy used, and the leakage current value obtained. It is important to mention that analyzed topologies present a variation of the leakage current between 0 to 180 mA. Finally, the trends, problems, and researches on transformerless grid-connected PV systems are discussed.

Analytical study and simulation of a transformer-less photovoltaic grid-connected inverter with a delta-type tri-direction clamping cell for leakage current elimination

2018 ◽  
Vol 37 (2) ◽  
pp. 814-831 ◽  
Author(s):  
Tohid Jalilzadeh ◽  
Mehrdad Tarafdar Hagh ◽  
Mehran Sabahi
Keyword(s):  
Power Systems ◽  
Leakage Current ◽  
Control Method ◽  
Harmonic Distortion ◽  
Common Mode ◽  
Content Type ◽  
Low Leakage ◽  
Common Mode Voltage ◽  
Power Switches ◽  
The Common

PurposeThis paper aims to propose a new transformer-less inverter structure to reduce the common-mode leakage current in grid-connected photovoltaic (PV) systems. Design/methodology/approachThe proposed circuit structure is the same as the conventional full-bridge inverter with three additional power switches in a triangular structure. These three power switches are between the bridge and the output filter, and they mitigate the common-mode leakage current flowing toward the PV panels’ capacitors. The common-mode leakage current mitigation is done through the three-direction clamping cell (TDCC) concept. By clamping the common-mode voltage to the middle voltage of the DC-link capacitors, the leakage current and the total harmonic distortion (THD) of the injected current to the grid is effectively reduced. Therefore, the efficiency is improved. FindingsThe switching modes and the control method are introduced. A comparison is carried out between the proposed structure and other solutions in the literature. The proposed topology and its respective control method are simulated by PSCAD/EMTDC software. The simulation results validate the advantages of the presented structure such as clamping the common-mode voltage and reducing leakage current and THD of injected current to the grid. Originality/valuePresenting a single phase-improved inverter structure with low-leakage current for grid-connected PV power systems represents a significant original contribution to this work. The proposed structure can inject a sinusoidal current with low THD to the AC grid, and the power factor is unity on the AC side. In the half positive cycle, one of the switches in the TDCC is turned off under zero current. Besides, one of the other switches in TDCC is turned on with zero voltage and, therefore, its turn-on switching losses are zero. The efficiency of the proposed topology is high because of the reduction of leakage current and power losses. Accordingly, the presented topology can be a good solution to the leakage current elimination.

scholarly journals Common-Mode Voltage Harmonic Reduction in Variable Speed Drives Applying a Variable-Angle Carrier Phase-Displacement PWM Method

Energies ◽  
2021 ◽  
Vol 14 (10) ◽  
pp. 2929
Author(s):  
Abraham Marquez Alcaide ◽  
Vito Giuseppe Monopoli ◽  
Xuchen Wang ◽  
Jose I. Leon ◽  
Giampaolo Buticchi ◽  
...  
Keyword(s):  
Carrier Phase ◽  
Harmonic Distortion ◽  
Harmonic Spectrum ◽  
Hydraulic Systems ◽  
Variable Speed ◽  
Common Mode ◽  
Variable Speed Drives ◽  
Phase Displacement ◽  
Common Mode Voltage ◽  
External Component

Electric variable speed drives (VSD) have been replacing mechanic and hydraulic systems in many sectors of industry and transportation because of their better performance and reduced cost. However, the electric systems still face the issue of being considered less reliable than the mechanical ones. For this reason, researchers have been actively investigating effective ways to increase the reliability of such systems. This paper is focused on the analysis of the common-mode voltage (CMV) generated by the operation of the VSDs which directly affects to the lifetime and reliability of the complete system. The method is based on the mathematical description of the harmonic spectrum of the CMV depending on the PWM method implementation. A generalized PWM method where the carriers present a variable phase-displacement is developed. As a result of the presented analysis, the CMV reduction is achieved by applying the PWM method with optimal carrier phase-displacement angles without any external component and/or passive filtering technique. The optimal values of the carrier phase-displacement angles are obtained considering the minimization of the CMV total harmonic distortion. The resulting method is easily implementable on mostly off-the-shelf mid-range micro-controller control platforms. The strategy has been evaluated in a scaled-down experimental setup proving its good performance.

scholarly journals Opposite Triangle Carrier with SVPWM for Common-Mode Voltage Reduction in Dual Three Phase Motor Drives

Energies ◽  
2021 ◽  
Vol 14 (2) ◽  
pp. 282
Author(s):  
Seon-Ik Hwang ◽  
Jang-Mok Kim
Keyword(s):  
Electromagnetic Interference ◽  
Pulse Width Modulation ◽  
Motor Drives ◽  
Common Mode ◽  
Pwm Inverter ◽  
Common Mode Voltage ◽  
Voltage Vector ◽  
Three Phase ◽  
The Common ◽  
Zero Voltage

The common-mode voltage (CMV) generated by the switching operation of the pulse width modulation (PWM) inverter leads to bearing failure and electromagnetic interference (EMI) noises. To reduce the CMV, it is necessary to reduce the magnitude of dv/dt and change the frequency of the CMV. In this paper, the range of the CMV is reduced by using opposite triangle carrier for ABC and XYZ winding group, and the change in frequency in the CMV is reduced by equalizing the dwell time of the zero voltage vector on ABC and XYZ winding group of dual three phase motor.

scholarly journals Optimization of TSPWM for Common-Mode Voltage Reduction in Vehicular Electric Drive System

2021 ◽  
Vol 13 (1) ◽  
pp. 5
Author(s):  
Shang Jiang ◽  
Yuan Wang
Keyword(s):  
Electric Drive ◽  
Drive System ◽  
Modulation Method ◽  
Time Interval ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Electric Drive System ◽  
The Common ◽  
Modulation Methods ◽  
Zero Voltage

Common-mode voltage can be reduced effectively by optimized modulation methods without increasing additional costs. However, the existing methods cannot satisfy the requirements of the vehicular electric-drive application. This paper optimizes the tri-state voltage modulation method to reduce the common-mode voltage for vehicular electric drive system applications. Firstly, the discontinuous switching issue during sector transition is analyzed. Under the limit of two switching times in one period, multiple alignments combination is proposed to address that issue. Secondly, the zero-voltage time intervals in different modulation ranges are explored. This paper proposes an unsymmetric translation method to reconstruct the voltage vector, and then the minimum zero-voltage time interval is controlled to enough value for safe switching. Finally, the proposed methods have been validated through experiments on a vehicular electric drive system. The results show that the common-mode voltage can be reduced effectively in the whole range with the optimized tri-state voltage modulation method.

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