scholarly journals Design of W-Band GaN-on-Silicon Power Amplifier Using Low Impedance Lines

2021 ◽  
Vol 11 (19) ◽  
pp. 9017
Author(s):  
Jinho Jeong ◽  
Yeongmin Jang ◽  
Jongyoun Kim ◽  
Sosu Kim ◽  
Wansik Kim

In this paper, a high-power amplifier integrated circuit (IC) in gallium-nitride (GaN) on silicon (Si) technology is presented at a W-band (75–110 GHz). In order to mitigate the losses caused by relatively high loss tangent of Si substrate compared to silicon carbide (SiC), low-impedance microstrip lines (20–30 Ω) are adopted in the impedance matching networks. They allow for the impedance transformation between 50 Ω and very low impedances of the wide-gate transistors used for high power generation. Each stage is matched to produce enough power to drive the next stage. A Lange coupler is employed to combine two three-stage common source amplifiers, providing high output power and good input/output return loss. The designed power amplifier IC was fabricated in the commercially available 60 nm GaN-on-Si high electron mobility transistor (HEMT) foundry. From on-wafer probe measurements, it exhibits the output power higher than 26.5 dBm and power added efficiency (PAE) higher than 8.5% from 88 to 93 GHz with a large-signal gain > 10.5 dB. Peak output power is measured to be 28.9 dBm with a PAE of 13.3% and a gain of 9.9 dB at 90 GHz, which corresponds to the power density of 1.94 W/mm. To the best of the authors’ knowledge, this result belongs to the highest output power and power density among the reported power amplifier ICs in GaN-on-Si HEMT technologies operating at the W-band.

Circuit World ◽  
2020 ◽  
Vol 46 (4) ◽  
pp. 243-248
Author(s):  
Min Liu ◽  
Panpan Xu ◽  
Jincan Zhang ◽  
Bo Liu ◽  
Liwen Zhang

Purpose Power amplifiers (PAs) play an important role in wireless communications because they dominate system performance. High-linearity broadband PAs are of great value for potential use in multi-band system implementation. The purpose of this paper is to present a cascode power amplifier architecture to achieve high power and high efficiency requirements for 4.2∼5.4 GHz applications. Design/methodology/approach A common emitter (CE) configuration with a stacked common base configuration of heterojunction bipolar transistor (HBT) is used to achieve high power. T-type matching network is used as input matching network. To increase the bandwidth, the output matching networks are implemented using the two L-networks. Findings By using the proposed method, the stacked PA demonstrates a maximum saturated output power of 26.2 dBm, a compact chip size of 1.17 × 0.59 mm2 and a maximum power-added efficiency of 46.3 per cent. The PA shows a wideband small signal gain with less than 3 dB variation over working frequency. The saturated output power of the proposed PA is higher than 25 dBm between 4.2 and 5.4 GHz. Originality/value The technology adopted for the design of the 4.2-to-5.4 GHz stacked PA is the 2-µm gallium arsenide HBT process. Based on the proposed method, a better power performance of 3 dB improvement can be achieved as compared with the conventional CE or common-source amplifier because of high output stacking impedance.


2004 ◽  
Vol 14 (03) ◽  
pp. 738-744 ◽  
Author(s):  
K. K. CHU ◽  
P. C. CHAO ◽  
J. A. WINDYKA

High power AlGaN/GaN HEMTs on free-standing GaN substrates with excellent stability have been demonstrated for the first time. When operated at a drain bias of 50V, devices without a field plate showed a record CW output power density of 10.0W/mm at 10GHz with an associated power-added efficiency of 45%. The efficiency reaches a maximum of 58% with an output power density of 5.5W/mm under a drain bias of 25V at 10GHz. Long-term stability of device RF operation was also examined. Under ambient conditions, devices biased at 25V and driven at 3dB gain compression remained stable at least up to 1,000 hours, degrading only by 0.35dB in output power. Such results clearly demonstrate the feasibility of GaN - on - GaN HEMT as an alternative device technology to the GaN - on - SiC HEMT in supporting reliable, high performance microwave power applications.


2010 ◽  
Vol 2 (3-4) ◽  
pp. 317-324 ◽  
Author(s):  
Paul Saad ◽  
Christian Fager ◽  
Hossein Mashad Nemati ◽  
Haiying Cao ◽  
Herbert Zirath ◽  
...  

This paper presents the design and implementation of an inverse class-F power amplifier (PA) using a high power gallium nitride high electron mobility transistor (GaN HEMT). For a 3.5 GHz continuous wave signal, the measurement results show state-of-the-art power-added efficiency (PAE) of 78%, a drain efficiency of 82%, a gain of 12 dB, and an output power of 12 W. Moreover, over a 300 MHz bandwidth, the PAE and output power are maintained at 60% and 10 W, respectively. Linearized modulated measurements using 20 MHz bandwidth long-term evolution (LTE) signal with 11.5 dB peak-to-average ratio show that −42 dBc adjacent channel power ratio (ACLR) is achieved, with an average PAE of 30%, −47 dBc ACLR with an average PAE of 40% are obtained when using a WCDMA signal with 6.6 dB peak-to-average ratio (PAR).


1992 ◽  
Vol 281 ◽  
Author(s):  
Pin Ho ◽  
M. Y. Kao ◽  
P. C. Chao ◽  
K. H. G. Duh ◽  
P. M. Smith ◽  
...  

ABSTRACTHigh electron mobility transistors (HEMTs) based on the InAlAs/InGaAs heterostructure have been grown on InP by molecular beam epitaxy. At room temperature, typical sheet charge densities of 2.1–3.0×1012 cm−2 and Hall electron mobilities over 10000 cm2 /V-s are obtained. An electron mobility as high as 13000 cm2 /V-s is achieved with a pseudomorphic Iny Ga1−y As channel and a y value of 0.70.HEMTs with a T- or Γ-shaped gate and with gate lengths ranging from 0.1–0.25 urn have been fabricated. A record low noise figure of 0.7 dB with an associated gain of 8.6 dB at 62 GHz has been achieved with 0.1 μm Γ-gate devices, while T-gate devices exhibit a minimum noise figure of 1.2 dB with 7.2 dB associated gain at 94 GHz. Separately, a record fmax value of 455 GHz was determined by extrapolating at -6 dB/octave from the measured gain of 13.6 dB at 95 GHz.Power HEMTs using a double heterojunction structure exhibit a record peak power-added efficiency (P.A.E.) of 49% with 8.6 dB power gain and 0.30 W/mm power density measured at 60 GHz. When biased and tuned for maximum output power, our best 60 GHz output power density to date is 0.52 W/mm with 33% P.A.E. and 5.9 dB power gain using a single heterojunction HEMT scheme with pseudomorphic channel. A similar device also yields peak P.A.E. of 26% with 0.20 W/mm power density and 4.9 dB gain at 94 GHz. These results represent the highest P.A.E.S and power gains ever reported for any transistor at these frequencies.


Author(s):  
Rocco Giofre ◽  
Ferdinando Costanzo ◽  
Sergio Colangeli ◽  
Walter Ciccognani ◽  
Manuela Sotgia ◽  
...  

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 899
Author(s):  
Jihoon Kim

A broadband millimeter-wave (mmWave) power amplifier (PA) was implemented using a modified 2D distributed power combining technique. The proposed power combining was based on a single-ended dual-fed distributed combining (SEDFDC) design technique using zero-phase shifting (ZPS) transmission lines. To improve the input/output power distribution of each power cell within a wide frequency range, N/2-way power dividers/combiners were inserted into the distributed combining structure. Modified ZPS lines also simplified the combining structure and curbed phase variation according to the frequency. These modifications enabled power combining cells to increase without degrading the power bandwidth. The proposed PA was fabricated with a commercial 0.15 μm GaAs pseudo high electron-mobility transistor (pHEMT) monolithic microwave-integrated circuit (MMIC) process. It exhibited 20.3 to 24.2 dBm output power (Pout), 12.9 to 21.8 dB power gain, and 5.2% to 12.7% power-added efficiency (PAE) between 26 and 56 GHz.


Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 890
Author(s):  
Kyu-Jin Choi ◽  
Jae-Hyun Park ◽  
Seong-Kyun Kim ◽  
Byung-Sung Kim

A K-band complementary metal-oxide-semiconductor (CMOS) differential cascode power amplifier is designed with the thin-oxide field effect transistor (FET) common source (CS) stage and thick-oxide FET common gate (CG) stage. Use of the thick-oxide CG stage affords the high supply voltage to 3.7 V and enables the high output power. Additionally, simple analysis shows that the gain degradation due to the low cut-off frequency of the thick-oxide CG FET can be compensated by the high output resistance of the thick-oxide FET if the inter-stage node is neutralized. The measured results of the proposed power amplifier demonstrate the saturated output power of the 23.3 dBm with the 31.3% peak power added efficiency (PAE) at 24 GHz frequency. The chip is fabricated in 65-nm low power (LP) CMOS technology and the chip size including all pads is 700 μm × 630 μm.


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