scholarly journals Performance and error analysis of Knill's postselection scheme in a two-dimensional architecture

2014 ◽  
Vol 14 (9&10) ◽  
pp. 807-822
Author(s):  
Ching-Yi Lai ◽  
Gerardo Paz ◽  
Martin Suchara ◽  
Todd A. Brun

Knill demonstrated a fault-tolerant quantum computation scheme based on concatenated error-detecting codes and postselection with a simulated error threshold of $3\%$ over the depolarizing channel. We show how to use Knill's postselection scheme in a practical two-dimensional quantum architecture that we designed with the goal to optimize the error correction properties, while satisfying important architectural constraints. In our 2D architecture, one logical qubit is embedded in a tile consisting of $5\times 5$ physical qubits. The movement of these qubits is modeled as noisy SWAP gates and the only physical operations that are allowed are local one- and two-qubit gates. We evaluate the practical properties of our design, such as its error threshold, and compare it to the concatenated Bacon-Shor code and the concatenated Steane code. Assuming that all gates have the same error rates, we obtain a threshold of $3.06\times 10^{-4}$ in a local adversarial stochastic noise model, which is the highest known error threshold for concatenated codes in 2D. We also present a Monte Carlo simulation of the 2D architecture with depolarizing noise and we calculate a pseudo-threshold of about $0.1\%$. With memory error rates one-tenth of the worst gate error rates, the threshold for the adversarial noise model, and the pseudo-threshold over depolarizing noise, are $4.06\times 10^{-4}$ and $0.2\%$, respectively. In a hypothetical technology where memory error rates are negligible, these thresholds can be further increased by shrinking the tiles into a $4\times 4$ layout.

2009 ◽  
Vol 9 (7&8) ◽  
pp. 666-682

(pp0666-0682) F.M. Spedalieri and V.P. Roychowdhury We analyze the latency of fault-tolerant quantum computing based on the 9-qubit Bacon-Shor code using a local, two-dimensional architecture. We embed the data qubits in a 7 by 7 array of physical qubits, where the extra qubits are used for ancilla preparation and qubit transportation by means of a SWAP chain. The latency is reduced with respect to a similar implementation using Steane's 7-qubit code~\cite{svore2007a}. Furthermore, the error threshold is also improved to $2.02 \times 10^{-5}$, when memory errors are taken to be one tenth of the gate error rates.


Nature ◽  
2021 ◽  
Vol 595 (7867) ◽  
pp. 383-387
Author(s):  
◽  
Zijun Chen ◽  
Kevin J. Satzinger ◽  
Juan Atalaya ◽  
Alexander N. Korotkov ◽  
...  

AbstractRealizing the potential of quantum computing requires sufficiently low logical error rates1. Many applications call for error rates as low as 10−15 (refs. 2–9), but state-of-the-art quantum platforms typically have physical error rates near 10−3 (refs. 10–14). Quantum error correction15–17 promises to bridge this divide by distributing quantum logical information across many physical qubits in such a way that errors can be detected and corrected. Errors on the encoded logical qubit state can be exponentially suppressed as the number of physical qubits grows, provided that the physical error rates are below a certain threshold and stable over the course of a computation. Here we implement one-dimensional repetition codes embedded in a two-dimensional grid of superconducting qubits that demonstrate exponential suppression of bit-flip or phase-flip errors, reducing logical error per round more than 100-fold when increasing the number of qubits from 5 to 21. Crucially, this error suppression is stable over 50 rounds of error correction. We also introduce a method for analysing error correlations with high precision, allowing us to characterize error locality while performing quantum error correction. Finally, we perform error detection with a small logical qubit using the 2D surface code on the same device18,19 and show that the results from both one- and two-dimensional codes agree with numerical simulations that use a simple depolarizing error model. These experimental demonstrations provide a foundation for building a scalable fault-tolerant quantum computer with superconducting qubits.


2006 ◽  
Vol 6 (6) ◽  
pp. 516-526
Author(s):  
P.J. Salas

The error correcting capabilities of the Calderbank-Shor-Steane [[7,1,3]] quantum code, together with a fault-tolerant syndrome extraction by means of several ancilla states, have been numerically studied. A simple probability expression to characterize the code ability for correcting an encoded qubit has been considered. This probability, as a correction quality criterion, permits the error correction capabilities among different recovery schemes to be compared. The memory error threshold is calculated by means of the best method of those considered.


2008 ◽  
Vol 86 (4) ◽  
pp. 533-540
Author(s):  
A G Fowler ◽  
W F Thompson ◽  
Z Yan ◽  
A M Stephens ◽  
B L.T. Plourde ◽  
...  

Constructing a fault-tolerant quantum computer is a daunting task. Given any design, it is possible to determine the maximum error rate of each type of component that can be tolerated while still permitting arbitrarily large-scale quantum computation. It is an under-appreciated fact that including an appropriately designed mechanism enabling long-range qubit coupling or transport substantially increases the maximum tolerable error rates of all components. With this thought in mind, we take the superconducting flux qubit coupling mechanism described in Plourde et al. (Phys. Rev. B, 70, 140501(R) (2004)) and extend it to allow approximately 500~MHz coupling of square flux qubits, 50 µm a side, at a distance of up to several mm. This mechanism is then used as the basis of two scalable architectures for flux qubits taking into account crosstalk and fault-tolerant considerations such as permitting a universal set of logical gates, parallelism, measurement and initialization, and data mobility.PACS No.: 03.67.Lx


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