Modeling and Simulation Speed-Up of Plasma Actuators Implementing Reconfigurable Hardware

AIAA Journal ◽  
2018 ◽  
Vol 56 (8) ◽  
pp. 3035-3046 ◽  
Author(s):  
Abbas Ebrahimi ◽  
Mohammad Zandsalimy
2014 ◽  
Vol 599-601 ◽  
pp. 652-655 ◽  
Author(s):  
Shao Jun Bo ◽  
Hao Zhu ◽  
Qing Huai Ye

We studied key technologies of the rigid-flexible coupling systems modeling and simulation based on the theory of multi-body dynamics and virtual prototyping technology. The study proposed concrete measures to ensure the accuracy of the simulation to short the simulation time and improve simulation speed. It greatly improved the reliability and interoperability of research used three software UG, Ansys and Adams on rigid-flexible coupling system and found the existing issue of key parts of the design department, provided a strong quantitative basis for optimizing the loader working device.


2020 ◽  
Vol 8 (1) ◽  
Author(s):  
Sa'ed Abed

Digital image processing is known as computer manipulation of image, which includes algorithms like image enhancement and target reorganization. Some of these algorithms involve operations like convolution and edge detection, which requires high computation. Generally, the software running on processor performs these manipulations. To achieve higher computation performance in terms of execution time, these algorithms are implemented on reconfigurable hardware like FPGA. One can implement parallel architecture and pipelined architecture on FPGA to gain speed up.  In this work, we provide a detailed description of implementing edge detection algorithm on SGI–RC100 platform. The algorithm is implemented using ANSI-C to manipulate the host program and Mitrion–C language. Mitrion–C offers efficient way to write code for parallel and pipelined architecture to preform edge detection. Then, the algorithm is tested on Intel Intanium 2 based architecture and compared its execution time with RC 100 platform based algorithm to check the speed up gain by FPGA based algorithm. The experimental results showed that the speed of the reconfigurable hardware FPGA based algorithm outperformed the software-based approach by more than 50 times.


2021 ◽  
pp. 193229682110322
Author(s):  
Jana Schmitzer ◽  
Carolin Strobel ◽  
Ronald Blechschmidt ◽  
Adrian Tappe ◽  
Heiko Peuscher

Background: Numerical simulations, also referred to as in silico trials, are nowadays the first step toward approval of new artificial pancreas (AP) systems. One suitable tool to run such simulations is the UVA/Padova Type 1 Diabetes Metabolic Simulator (T1DMS). It was used by Toffanin et al. to provide data about safety and efficacy of AndroidAPS, one of the most wide-spread do-it-yourself AP systems. However, the setup suffered from slow simulation speed. The objective of this work is to speed up simulation by implementing the algorithm directly in MATLAB®/Simulink®. Method: Firstly, AndroidAPS is re-implemented in MATLAB® and verified. Then, the function is incorporated into T1DMS. To evaluate the new setup, a scenario covering 2 days in real time is run for 30 virtual patients. The results are compared to those presented in the literature. Results: Unit tests and integration tests proved the equivalence of the new implementation and the original AndroidAPS code. Simulation of the scenario required approximately 15 minutes, corresponding to a speed-up factor of roughly 1000 with respect to real time. The results closely resemble those presented by Toffanin et al. Discrepancies were to be expected because a different virtual population was considered. Also, some parameters could not be extracted from and harmonized with the original setup. Conclusions: The new implementation facilitates extensive in silico trials of AndroidAPS due to the significant reduction of runtime. This provides a cheap and fast means to test new versions of the algorithm before they are shared with the community.


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