SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores

2015 ◽  
Author(s):  
Syed Saif Abrar ◽  
Maksim Jenihhin ◽  
Jaan Raik
Keyword(s):  
Simulation Speed ◽  
Speed Up ◽  
Ip Cores

scholarly journals AC_ICAP: A Flexible High Speed ICAP Controller

2015 ◽  
Vol 2015 ◽  
pp. 1-15 ◽  
Author(s):  
Luis Andres Cardona ◽  
Carles Ferrer
Keyword(s):  
High Speed ◽  
Access Port ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Speed Up ◽  
Run Time ◽  
Ip Cores ◽  
Similar Solutions ◽  
Internal Configuration ◽  
Run Time Reconfiguration

The Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in Xilinx SRAM-based Field Programmable Gate Arrays (FPGAs). We developed a new high speed ICAP controller, named AC_ICAP, completely implemented in hardware. In addition to similar solutions to accelerate the management of partial bitstreams and frames, AC_ICAP also supports run-time reconfiguration of LUTs without requiring precomputed partial bitstreams. This last characteristic was possible by performing reverse engineering on the bitstream. Besides, we adapted this hardware-based solution to provide IP cores accessible from the MicroBlaze processor. To this end, the controller was extended and three versions were implemented to evaluate its performance when connected to Peripheral Local Bus (PLB), Fast Simplex Link (FSL), and AXI interfaces of the processor. In consequence, the controller can exploit the flexibility that the processor offers but taking advantage of the hardware speed-up. It was implemented in both Virtex-5 and Kintex7 FPGAs. Results of reconfiguration time showed that run-time reconfiguration of single LUTs in Virtex-5 devices was performed in less than 5 μs which implies a speed-up of more than 380x compared to the Xilinx XPS_HWICAP controller.

Efficient Realization of Fixed-Point Binary and Ternary Adders on FPGAs

2016 ◽  
Vol 26 (04) ◽  
pp. 1750053
Author(s):  
Burhan Khurshid ◽  
Roohie Naaz
Keyword(s):  
Signal Processing ◽  
Fixed Point ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
Boolean Networks ◽  
Full Potential ◽  
Speed Up ◽  
Ip Cores ◽  
Efficient Realization

Binary and ternary adders are frequently used to speed-up many digital signal processing (DSP) operations like multiplication, compression, filtering, convolution, etc. FPGA realization of these circuits uses a combination of look-up tables (LUTs) and carry-chains. Alternatively, inbuilt operators and parameterizable IP cores provide an efficient means of implementing these circuits. However, the realization is not optimal in the sense that the full potential of the underlying resources is not utilized. In this paper, we use technology-dependent approaches to restructure the Boolean networks corresponding to these circuits. The restructured networks are then mapped optimally onto the FPGA fabric using minimum possible resources. Our analysis shows a subsequent speed-up in the performance of these circuits when compared to different conventional and existing approaches.

scholarly journals Efficient Closed Loop Simulation of Do-It-Yourself Artificial Pancreas Systems

2021 ◽  
pp. 193229682110322
Author(s):  
Jana Schmitzer ◽  
Carolin Strobel ◽  
Ronald Blechschmidt ◽  
Adrian Tappe ◽  
Heiko Peuscher
Keyword(s):  
Real Time ◽  
In Silico ◽  
Closed Loop ◽  
Artificial Pancreas ◽  
Virtual Patients ◽  
Simulation Speed ◽  
Virtual Population ◽  
Speed Up ◽  
Do It Yourself

Background: Numerical simulations, also referred to as in silico trials, are nowadays the first step toward approval of new artificial pancreas (AP) systems. One suitable tool to run such simulations is the UVA/Padova Type 1 Diabetes Metabolic Simulator (T1DMS). It was used by Toffanin et al. to provide data about safety and efficacy of AndroidAPS, one of the most wide-spread do-it-yourself AP systems. However, the setup suffered from slow simulation speed. The objective of this work is to speed up simulation by implementing the algorithm directly in MATLAB®/Simulink®. Method: Firstly, AndroidAPS is re-implemented in MATLAB® and verified. Then, the function is incorporated into T1DMS. To evaluate the new setup, a scenario covering 2 days in real time is run for 30 virtual patients. The results are compared to those presented in the literature. Results: Unit tests and integration tests proved the equivalence of the new implementation and the original AndroidAPS code. Simulation of the scenario required approximately 15 minutes, corresponding to a speed-up factor of roughly 1000 with respect to real time. The results closely resemble those presented by Toffanin et al. Discrepancies were to be expected because a different virtual population was considered. Also, some parameters could not be extracted from and harmonized with the original setup. Conclusions: The new implementation facilitates extensive in silico trials of AndroidAPS due to the significant reduction of runtime. This provides a cheap and fast means to test new versions of the algorithm before they are shared with the community.

Application Workload Modelling via Run-Time Performance Statistics

2013 ◽  
Vol 4 (2) ◽  
pp. 1-35
Author(s):  
Subayal Khan ◽  
Jukka Saastamoinen ◽  
Jyrki Huusko ◽  
Juha-Pekka Soininen ◽  
Jari Nurmi
Keyword(s):  
Integrated Circuit ◽  
System Level ◽  
Simulation Speed ◽  
Reduced Modeling ◽  
Workload Generation ◽  
Run Time ◽  
Performance Statistics ◽  
Ip Cores ◽  
And Performance ◽  
Workload Models

Modern mobile nomadic devices for example internet tablets and high end mobile phones support diverse distributed and stand-alone applications that were supported by single devices a decade back. Furthermore the complex heterogeneous platforms supporting these applications contain multi-core processors, hardware accelerators and IP cores and all these components can possibly be integrated into a single integrated circuit (chip). The high complexity of both the platform and the applications makes the design space very complex due to the availability of several alternatives. Therefore the system designer must be able to quickly evaluate the performance of different application architectures and implementations on potential platforms. The most popular technique employed nowadays is termed as system-level-performance evaluation which uses abstract workload and platform capacity models. The platform capacity models and application workload models reside at a higher abstraction-level. The platform and application workload models can be instantiated with reduced modeling effort and also operate at a higher simulation speed. This article presents a novel run-time statistics based application workload model extraction and platform configuration technique. This technique is called platform COnfiguration and woRkload generatIoN via code instrumeNtation and performAnce counters (CORINNA) which offers several advantages over compiler based technique called ABSINTH, and also provides automatic configuration of the platform processor models for example cache-hits and misses obtained during the application execution.

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