Heterogeneous Integration by Collective Die-To-Wafer Bonding

Heterogeneous integration of III-V compound semiconductors and Ge on the Si platform is one of the promising technologies for enhancing the performance of metal-oxide-semiconductor field effect transistors (MOSFETs) beyond the 10-nm technology node because of their high carrier mobilities. In addition, the III-Vs and Ge are also promising materials for photonic devices. Thus, we have investigated III-V/Ge device engineering for CMOS photonics, enabling monolithic integration of high-performance III-V/Ge CMOS transistors and III-V/Ge photonics on Si. The direct wafer bonding of III-V on Si has been investigated to form III-V on Insulator for III-V CMOS photonics. Extremely-thin-body InGaAs MOSFETs with the gate length of approximately 55 nm have successfully been demonstrated by using the wafer bonding. InP-based photonic-wire waveguide devices including micro bends, arrayed waveguide gratings, grating couplers, optical switches, and InGaAs photodetectors have also been demonstrated on the III-V-OI wafer. The gate stack formation on Ge is one of the critical issues for Ge MOSFETs. Recently, we have successfully demonstrated high-quality GeOx/Ge MOS interfaces formed by thermal oxidation and plasma oxidation. High-performance Ge pMOSFET and nMOSFET with thin EOT have been obtained using the GeOx/Ge MOS interfaces. We have also demonstrated that GeOx surface passivation is effective to reduce the dark current of Ge photodetectors in conjunction with gas-phase doped junction. We have also investigated strained SiGe optical modulators. We expect that compressive strain in SiGe enhances modulation efficiency, and an extremely small VπL of 0.033 V-cm is predicted. III-V/Ge heterogeneous integration is one of the promising ways for achieving ultrahigh performance electronic-photonic integrated circuits.

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Heterogeneous Integration of III-V Materials by Direct Wafer Bonding for High-Performance Electronics and Optoelectronics

IEEE Transactions on Electron Devices ◽

10.1109/ted.2021.3067273 ◽

2021 ◽

pp. 1-8

Author(s):

Daniele Caimi ◽

Preksha Tiwari ◽

Marilyne Sousa ◽

Kirsten E. Moselund ◽

Cezar B. Zota

Keyword(s):

Wafer Bonding ◽

High Performance ◽

Heterogeneous Integration ◽

Direct Wafer Bonding

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High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

Frontiers in Materials ◽

10.3389/fmats.2015.00028 ◽

2015 ◽

Vol 2 ◽

Cited By ~ 13

Author(s):

Xianshu Luo ◽

Yulian Cao ◽

Junfeng Song ◽

Xiaonan Hu ◽

Yuanbing Cheng ◽

...

Keyword(s):

Integrated Circuits ◽

High Throughput ◽

Wafer Bonding ◽

Heterogeneous Integration ◽

Optoelectronic Integrated Circuits ◽

Hybrid Lasers ◽

Bonding Technology

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Si/InP Heterogeneous Integration Techniques from the Wafer-Scale (Hybrid Wafer Bonding) to the Discrete Transistor (Micro-Transfer Printing)

2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2018.8640196 ◽

2018 ◽

Cited By ~ 2

Author(s):

Andrew D. Carter ◽

Miguel E. Urteaga ◽

Zachary M. Griffith ◽

Kang-Jin Lee ◽

Jonathan Roderick ◽

...

Keyword(s):

Wafer Bonding ◽

Heterogeneous Integration ◽

Transfer Printing ◽

Wafer Scale ◽

Integration Techniques

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Moiré-Based Alignment Using Centrosymmetric Grating Marks for High-Precision Wafer Bonding

Micromachines ◽

10.3390/mi10050339 ◽

2019 ◽

Vol 10 (5) ◽

pp. 339 ◽

Cited By ~ 1

Author(s):

Boyan Huang ◽

Chenxi Wang ◽

Hui Fang ◽

Shicheng Zhou ◽

Tadatomo Suga

Keyword(s):

High Precision ◽

Wafer Bonding ◽

Alignment Accuracy ◽

Heterogeneous Integration ◽

Alignment Method ◽

Wafer Level ◽

Bonding System ◽

Alignment System ◽

Working Principle ◽

Better Than

High-precision aligned wafer bonding is essential to heterogeneous integration, with the device dimension reduced continuously. To get the alignment more accurately and conveniently, we propose a moiré-based alignment method using centrosymmetric grating marks. This method enables both coarse and fine alignment steps without requiring additional conventional cross-and-box alignment marks. Combined with an aligned wafer bonding system, alignment accuracy better than 300 nm (3σ) was achieved after bonding. Furthermore, the working principle of the moiré-based alignment for the backside alignment system was proposed to overcome the difficulty in bonding of opaque wafers. We believe this higher alignment accuracy is feasible to satisfy more demanding requirements in wafer-level stacking technologies.

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Heterogeneous Integration of a 300mm Silicon Photonics-CMOS Wafer Stack by Direct Oxide Bonding and Via-last 3D Interconnection

International Symposium on Microelectronics ◽

10.4071/isom-2015-tha35 ◽

2015 ◽

Vol 2015 (1) ◽

pp. 000621-000626 ◽

Cited By ~ 3

Author(s):

Colin McDonough ◽

Doug La Tulipe ◽

Dan Pascual ◽

Paul Tariello ◽

John Mucci ◽

...

Keyword(s):

Wafer Bonding ◽

Silicon Photonics ◽

Heterogeneous Integration ◽

Production Environment ◽

3D Integration ◽

Si Photonics ◽

Electrical Connections ◽

First Time ◽

Low Capacitance

A fully functional Si photonics and 65-nm CMOS heterogeneous 3D integration is demonstrated for the first time in a 300mm production environment. Direct oxide wafer bonding was developed to eliminate voids between SOI photonics and bulk Si CMOS wafers. A via-last, Cu through-oxide via (TOV) 3D integration was developed for low capacitance electrical connections with no impact on CMOS performance. 3D yield approaching 100% was demonstrated on >20,000 via chains.

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