scholarly journals Thermal-Cycling-aware Dynamic Reliability Management in Many-Core System-on-Chip

2020 ◽  
Author(s):  
Mohammad-Hashem Haghbayan ◽  
Antonio Miele ◽  
Zhuo Zou ◽  
Hannu Tenhunen ◽  
Juha Plosila
Keyword(s):  
Thermal Cycling ◽  
System On Chip ◽  
Core System ◽  
Dynamic Reliability ◽  
Reliability Management ◽  
On Chip ◽  
Many Core

ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform

2017 ◽  
Vol 54 ◽  
pp. 60-74 ◽  
Author(s):  
Alireza Monemi ◽  
Jia Wei Tang ◽  
Maurizio Palesi ◽  
Muhammad N. Marsono
Keyword(s):  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Core System ◽  
On Chip ◽  
Many Core

Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant Graphs

2016 ◽  
Author(s):  
Zheng Wang ◽  
Alessandro Littarru ◽  
Emmanuel Ikechukwu Ugwu ◽  
Shazia Kanwal ◽  
Anupam Chattopadhyay
Keyword(s):  
Fault Tolerant ◽  
System On Chip ◽  
Chip Design ◽  
Core System ◽  
On Chip ◽  
Many Core

Many-core System-on-Chip: architectures and applications

2016 ◽  
Vol 43 ◽  
pp. 1-3 ◽  
Author(s):  
Mohamed Bakhouya ◽  
Masoud Daneshtalab ◽  
Maurizio Palesi ◽  
Hassan Ghasemzadeh
Keyword(s):  
System On Chip ◽  
Core System ◽  
On Chip ◽  
Many Core

scholarly journals FPGA-based many-core System-on-Chip design

2015 ◽  
Vol 39 (4-5) ◽  
pp. 302-312 ◽  
Author(s):  
M. Baklouti ◽  
Ph. Marquet ◽  
J.L. Dekeyser ◽  
M. Abid
Keyword(s):  
System On Chip ◽  
Chip Design ◽  
Core System ◽  
On Chip ◽  
Many Core

Temperature-Aware Task Scheduling for Dark Silicon Many-Core System-on-Chip

2019 ◽  
Author(s):  
Mohammed Sultan Mohammed ◽  
Ahlam Khaled Al-Dhamari ◽  
Ab Al-Hadi ab Rahman ◽  
Norlina Paraman ◽  
Ali A.M. Al-Kubati ◽  
...  
Keyword(s):  
Task Scheduling ◽  
System On Chip ◽  
Dark Silicon ◽  
Core System ◽  
On Chip ◽  
Many Core

Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC)

2010 ◽  
Vol 34 (2-4) ◽  
pp. 102-116 ◽  
Author(s):  
Hyun-min Kyung ◽  
Gi-ho Park ◽  
Jong Wook Kwak ◽  
Tae-jin Kim ◽  
Sung-Bae Park
Keyword(s):  
Performance Analysis ◽  
System On Chip ◽  
Core System ◽  
Design And Implementation ◽  
On Chip

Heterogenic Multi-Core System on Chip for Virtual Based Security

2019 ◽  
Author(s):  
Vladimir Ruchkin ◽  
Vladimir Fulin ◽  
Dmitry Pikulin ◽  
Aleksandr Taganov ◽  
Aleksandr Kolesenkov ◽  
...  
Keyword(s):  
System On Chip ◽  
Core System ◽  
On Chip

scholarly journals FPGA Prototyping of Micro-Blaze soft-processor based Multi-core System on Chip

2018 ◽  
Vol 7 (2.16) ◽  
pp. 57
Author(s):  
G Prasad Acharya ◽  
M Asha Rani
Keyword(s):  
Computer Aided Design ◽  
Processing System ◽  
System On Chip ◽  
Core System ◽  
Design Cycle ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip ◽  
Aided Design ◽  
Level Parallelism

The increased demand for processor-level parallelism has many-folded the challenges for SoC designers to design, simulate and verify/validate today’s Multi-core System-On-Chip (SoC) due to the increased system complexity. There is also a need to reduce the design cycle time to produce a complex multi-core SOC system thereby the product can be brought into the market within an affordable time. The Computer-Aided Design (CAD) tools and Field Programmable Gate Arrays (FPGAs) provide a solution for rapidly prototyping and validating the system. This paper presents an implementation of multi-core SoC consisting of 6 Xilinx Micro-Blaze soft-core processors integrated to the Zynq Processing System (PS) using IP Integrator and these cores will be communicated through AXI bus. The functionality of the system is verified using Micro-Blaze system debugger. The hardware framework for the implemented system is implemented and verified on FPGA.  

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