PHENIC: silicon photonic 3D-network-on-chip architecture for high-performance Heterogeneous many-core system-on-chip

2013 ◽  
Author(s):  
Achraf Ben Ahmed ◽  
Abderazek Ben Abdallah
Keyword(s):  
High Performance ◽  
Network On Chip ◽  
System On Chip ◽  
Core System ◽  
Silicon Photonic ◽  
3D Network ◽  
On Chip ◽  
Many Core

A Long-wire-connected and Multi-channel 3D Network-on-chip Design for Many-core System

2013 ◽  
Vol 11 (12) ◽  
Author(s):  
Tan Hai ◽  
Shahnawaz Talpur ◽  
Amir Mahmood Soomro ◽  
Chen Hong Mao
Keyword(s):  
Network On Chip ◽  
Chip Design ◽  
Core System ◽  
3D Network ◽  
On Chip ◽  
Many Core

ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform

2017 ◽  
Vol 54 ◽  
pp. 60-74 ◽  
Author(s):  
Alireza Monemi ◽  
Jia Wei Tang ◽  
Maurizio Palesi ◽  
Muhammad N. Marsono
Keyword(s):  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Core System ◽  
On Chip ◽  
Many Core

Design of Router Supporting Multiply Routing Algorithm for NoC

2014 ◽  
Vol 981 ◽  
pp. 431-434
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Chang Chun Dong ◽  
Lin Hai Cui
Keyword(s):  
Complex System ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Deterministic Routing ◽  
Key Features ◽  
Design Challenge ◽  
On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

scholarly journals Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
Alireza Monemi ◽  
Chia Yee Ooi ◽  
Muhammad Nadzir Marsono
Keyword(s):  
High Performance ◽  
Clock Cycle ◽  
Network On Chip ◽  
Operating Frequency ◽  
Low Latency ◽  
Core System ◽  
Low Area ◽  
Area Overhead ◽  
Logic Cells ◽  
On Chip

Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS). We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%~20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed NoC router achieves 2.3 times better performance compared to CONNECT.

A Fault-Tolerant Deflection Routing for Network-on-Chip

2016 ◽  
Vol 26 (03) ◽  
pp. 1750037 ◽  
Author(s):  
Xiaofeng Zhou ◽  
Lu Liu ◽  
Zhangming Zhu
Keyword(s):  
Fault Tolerant ◽  
Network On Chip ◽  
Deflection Routing ◽  
Core System ◽  
Routing Schemes ◽  
Routing Performance ◽  
Layout Area ◽  
On Chip ◽  
Many Core ◽  
Redundant Fault

Network-on-Chip (NoC) has become a promising design methodology for the modern on-chip communication infrastructure of many-core system. To guarantee the reliability of traffic, effective fault-tolerant scheme is critical to NoC systems. In this paper, we propose a fault-tolerant deflection routing (FTDR) to address faults on links and router by redundancy technique. The proposed FTDR employs backup links and a redundant fault-tolerant unit (FTU) at router-level to sustain the traffic reliability of NoC. Experimental results show that the proposed FTDR yields an improvement of routing performance and fault-tolerant capability over the reported fault-tolerant routing schemes in average flit deflection rate, average packet latency, saturation throughput and reliability by up to 13.5%, 9.8%, 10.6% and 17.5%, respectively. The layout area and power consumption are increased merely 3.5% and 2.6%.

scholarly journals Low power network on chip architectures: A survey

2020 ◽  
Vol 2 (3) ◽  
pp. 158-168
Author(s):  
Muhammad Raza Naqvi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Network Architecture ◽  
High Performance ◽  
State Of The Art ◽  
Network On Chip ◽  
System On Chip ◽  
Power Network ◽  
Network Routers ◽  
On Chip

Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.

Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant Graphs

2016 ◽  
Author(s):  
Zheng Wang ◽  
Alessandro Littarru ◽  
Emmanuel Ikechukwu Ugwu ◽  
Shazia Kanwal ◽  
Anupam Chattopadhyay
Keyword(s):  
Fault Tolerant ◽  
System On Chip ◽  
Chip Design ◽  
Core System ◽  
On Chip ◽  
Many Core
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