ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform

2017 ◽  
Vol 54 ◽  
pp. 60-74 ◽  
Author(s):  
Alireza Monemi ◽  
Jia Wei Tang ◽  
Maurizio Palesi ◽  
Muhammad N. Marsono
Keyword(s):  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Core System ◽  
On Chip ◽  
Many Core

Design of Router Supporting Multiply Routing Algorithm for NoC

2014 ◽  
Vol 981 ◽  
pp. 431-434
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Chang Chun Dong ◽  
Lin Hai Cui
Keyword(s):  
Complex System ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Deterministic Routing ◽  
Key Features ◽  
Design Challenge ◽  
On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

scholarly journals Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
Alireza Monemi ◽  
Chia Yee Ooi ◽  
Muhammad Nadzir Marsono
Keyword(s):  
High Performance ◽  
Clock Cycle ◽  
Network On Chip ◽  
Operating Frequency ◽  
Low Latency ◽  
Core System ◽  
Low Area ◽  
Area Overhead ◽  
Logic Cells ◽  
On Chip

Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS). We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%~20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed NoC router achieves 2.3 times better performance compared to CONNECT.

A Fault-Tolerant Deflection Routing for Network-on-Chip

2016 ◽  
Vol 26 (03) ◽  
pp. 1750037 ◽  
Author(s):  
Xiaofeng Zhou ◽  
Lu Liu ◽  
Zhangming Zhu
Keyword(s):  
Fault Tolerant ◽  
Network On Chip ◽  
Deflection Routing ◽  
Core System ◽  
Routing Schemes ◽  
Routing Performance ◽  
Layout Area ◽  
On Chip ◽  
Many Core ◽  
Redundant Fault

Network-on-Chip (NoC) has become a promising design methodology for the modern on-chip communication infrastructure of many-core system. To guarantee the reliability of traffic, effective fault-tolerant scheme is critical to NoC systems. In this paper, we propose a fault-tolerant deflection routing (FTDR) to address faults on links and router by redundancy technique. The proposed FTDR employs backup links and a redundant fault-tolerant unit (FTU) at router-level to sustain the traffic reliability of NoC. Experimental results show that the proposed FTDR yields an improvement of routing performance and fault-tolerant capability over the reported fault-tolerant routing schemes in average flit deflection rate, average packet latency, saturation throughput and reliability by up to 13.5%, 9.8%, 10.6% and 17.5%, respectively. The layout area and power consumption are increased merely 3.5% and 2.6%.

A Long-wire-connected and Multi-channel 3D Network-on-chip Design for Many-core System

2013 ◽  
Vol 11 (12) ◽  
Author(s):  
Tan Hai ◽  
Shahnawaz Talpur ◽  
Amir Mahmood Soomro ◽  
Chen Hong Mao
Keyword(s):  
Network On Chip ◽  
Chip Design ◽  
Core System ◽  
3D Network ◽  
On Chip ◽  
Many Core

Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant Graphs

2016 ◽  
Author(s):  
Zheng Wang ◽  
Alessandro Littarru ◽  
Emmanuel Ikechukwu Ugwu ◽  
Shazia Kanwal ◽  
Anupam Chattopadhyay
Keyword(s):  
Fault Tolerant ◽  
System On Chip ◽  
Chip Design ◽  
Core System ◽  
On Chip ◽  
Many Core

MAGALI: A Network-on-Chip based multi-core system-on-chip for MIMO 4G SDR

2010 ◽  
Author(s):  
Fabi Clermidy ◽  
Christian Bernard ◽  
Romain Lemaire ◽  
Jerome Martin ◽  
Ivan Miro-Panades ◽  
...  
Keyword(s):  
Network On Chip ◽  
System On Chip ◽  
Core System ◽  
On Chip

Many-core System-on-Chip: architectures and applications

2016 ◽  
Vol 43 ◽  
pp. 1-3 ◽  
Author(s):  
Mohamed Bakhouya ◽  
Masoud Daneshtalab ◽  
Maurizio Palesi ◽  
Hassan Ghasemzadeh
Keyword(s):  
System On Chip ◽  
Core System ◽  
On Chip ◽  
Many Core

scholarly journals FPGA-based many-core System-on-Chip design

2015 ◽  
Vol 39 (4-5) ◽  
pp. 302-312 ◽  
Author(s):  
M. Baklouti ◽  
Ph. Marquet ◽  
J.L. Dekeyser ◽  
M. Abid
Keyword(s):  
System On Chip ◽  
Chip Design ◽  
Core System ◽  
On Chip ◽  
Many Core

scholarly journals Implementation of ISLIP scheduler for NOC router on FPGA

2018 ◽  
Vol 7 (2.12) ◽  
pp. 268
Author(s):  
Priti M. Shahane ◽  
Narayan Pisharoty
Keyword(s):  
Internet Protocol ◽  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Single Chip ◽  
Dominant Component ◽  
Large Numbers ◽  
On Chip ◽  
Priority Encoder ◽  
Serial Line

Network on chip (NoC) effectively replaces a traditional bus based architecture in System on chip (SoC). The NoC provides a solution to the communication bottleneck of the bus based interconnection in SoC, where large numbers of Intellectual modules are integrated on a single chip for better performance. In NoC architecture, the router is a dominant component, which should provide contention free architecture with low latency. The router consists of input block, scheduler and crossbar switch. The design of scheduler leads the performance of the NoC router in terms of latency. Hence the starvation free scheduler is paramount importantin the NoC router design. iSLIP (Iterative serial line internet protocol) scheduler has programmable priority encoder which makes it fast and efficient scheduler over round robin arbiter. In this paper 2x4 NoC router using iSLIPscheduler is proposed. The proposed design is implemented using the Verilog programming on Xilinx Spartan 3 device. 

Sign in / Sign up

Export Citation Format

Share Document