scholarly journals Comparative evaluation of quasi-delay-insensitive asynchronous adders corresponding to return-to-zero and return-to-one handshaking

2018 ◽  
Vol 31 (1) ◽  
pp. 25-39 ◽  
Author(s):  
Padmanabhan Balasubramanian
Keyword(s):  
Power Dissipation ◽  
Comparative Evaluation ◽  
Average Power ◽  
Cmos Process ◽  
Strong Indication ◽  
Ripple Carry Adder ◽  
Carry Select Adder ◽  
Handshake Protocol ◽  
Handshake Protocols ◽  
Better Than

This article makes a comparative evaluation of quasi-delay-insensitive (QDI) asynchronous adders, realized using the delay-insensitive dual-rail code, which adhere to 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshake protocols. The QDI adders realized correspond to the following adder architectures: i) ripple carry adder, ii) carry lookahead adder, and iii) carry select adder. The QDI adders correspond to three different timing regimes viz. strong-indication, weak-indication, and early output. They are physically implemented using a 32/28nm CMOS process. The comparative evaluation shows that, overall, QDI adders which correspond to the 4-phase RTO handshake protocol are better than the QDI adder counterparts which correspond to the 4-phase RTZ handshake protocol in terms of latency, area, and average power dissipation.

CMOS-process-independent average power dissipation macromodelling

1995 ◽  
Vol 31 (16) ◽  
pp. 1337-1338 ◽  
Author(s):  
P.J. Mather ◽  
M. Brouwer ◽  
P. Hallam
Keyword(s):  
Power Dissipation ◽  
Average Power ◽  
Cmos Process

scholarly journals An Efficient VLSI Design of 32X32 bit Multiplier using Wallace Tree Algorithm in Vivado HLS and Xilinx ISE Software using VHDL

2020 ◽  
Vol 9 (7) ◽  
pp. 490-495
Keyword(s):  
Power Dissipation ◽  
Circuit Complexity ◽  
Vlsi Design ◽  
Digital Signal ◽  
Major Drawback ◽  
Tree Algorithm ◽  
Wallace Tree ◽  
Look Ahead ◽  
Ripple Carry Adder ◽  
Carry Select Adder

Multiplier is the most basic component present in any digital system. These multipliers are mainly used in Digital Signal and Image Processing applications. In applications like image detection latest sophisticated algorithms like CNN are used which contains MAC units in their design. The multiplier used in MAC unit requires huge memory, offers high latency and consumes more power. There are many algorithms such as Combinational, Sequential and Array Multiplication Algorithms which helps in designing Multiplier. The major drawback in all designs is circuit complexity. The problem of latency and power dissipation are also present. Considering all the drawbacks present in those algorithms this paper proposes the usage of Wallace Tree Algorithm which consumes less power and has low latency. Also, there are many ways to add the final stage of partial products generated such as Carry Look Ahead adder, Carry Select Adder etc. This paper uses both Carry Select Adder and Ripple Carry Adder for performing final addition of partial products. All previous partial products are added using Half adders and Full adders. The Multiplier is designed using VHDL in Xilinx ISE and Vivado Platform.

Updated Efficient Area -Carry Select Adder for Low Complexity D LATCH Configuration by disease identification in brain tumor hyper spectral image

2019 ◽  
Vol 14 ◽  
Author(s):  
Teresa V.V ◽  
Anand. B
Keyword(s):  
Research Work ◽  
Low Complexity ◽  
Propagation Delay ◽  
Maximum Speed ◽  
Hyper Spectral ◽  
Ripple Carry Adder ◽  
Minimum Power Consumption ◽  
Carry Select Adder ◽  
The Look ◽  
Propagation Result

Objective: In this research work presents an efficient way Carry Select Adder (CSLA) performance and estimation. The CSLA is utilized in several system to mitigate the issue of carry propagation delay that is happens by severally generating various carries and to get the sum, select a carry because of the uses of various pairs of RCA to provide the sum of the partial section also carry by consisting carry input but the CSLA isn't time economical, then by the multiplexers extreme total and carry is chosen in the selected section. Methodology: The fundamental plan of this work is to attain maximum speed and minimum power consumption by using Binary to Excess-1. Convertor rather than RCA within the regular CSLA. Here RCA denotes the Ripple Carry Adder section. At the span to more cut back the facility consumption, a method of CSLA with D LATCH is implemented during this research work. The look of Updated Efficient Area -Carry Select Adder (UEA-CSLA) is evaluated and intended in XILINX ISE design suite 14. 5 tools. This VLSI arrangement is utilized in picture preparing application by concluding the cerebrum tumor discovery. Conclusion: In this study, medicinal pictures estimation, investigation districts in the multi phantom picture isn't that much proficient to defeat this disadvantage here utilized hyper spectral picture method is presented a sifting procedure in VLSI innovation restriction of cerebrum tumor is performed Updated Efficient Area - Carry Select Adder propagation result dependent on Matrix Laboratory in the adaptation of R2018b.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

scholarly journals Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 369 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Nikos Mastorakis
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Performance Comparison ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Least Significant Bit ◽  
Design Metrics ◽  
Ripple Carry Adder ◽  
Speed Performance

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

scholarly journals Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

VLSI Design ◽  
2002 ◽  
Vol 15 (2) ◽  
pp. 547-553
Author(s):  
S. M. Rezaul Hasan ◽  
Yufridin Wahab
Keyword(s):  
Power Dissipation ◽  
Figure Of Merit ◽  
Low Voltage ◽  
Logic Gates ◽  
Base Layer ◽  
Cmos Process ◽  
Silicon Area ◽  
Dynamic Power ◽  
Analog Cmos ◽  
Power Delay Product

This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without any associated silicon-area penalty. In order to experimentally verify the reduction in power dissipation, original and reordered structures were fabricated using the MOSIS 2 μm N-well analog CMOS process which has a P-base layer for bipolar NPN option. Measured results shows a 20% reduction in the power dissipation for the transistor reordered structure, which is in close agreement with the simulation.

scholarly journals Approximate Adder: Lower-Part or Adder

2020 ◽  
Vol 9 (7) ◽  
pp. 1176-1180
Keyword(s):  
Real Time ◽  
Power Dissipation ◽  
High Performance ◽  
Building Blocks ◽  
Cmos Technology ◽  
Approximate Computing ◽  
Computing Technique ◽  
Ripple Carry Adder ◽  
Real Time Applications ◽  
Dsp Systems

High-performance VLSI systems are essential in real-time applications, in order to increase the performance of the VLSI systems, an approximate computing technique is followed where the performance of the circuit is enhanced by trading off it with a slight loss in the accuracy. These approximate circuits are used in error-tolerant applications, where output need not be accurate. This paper concentrates mainly on approximate adders, as they are major building blocks of DSP systems. The analysis of the Lower-part OR Adder for 4-bit addition and comparison of it with the precise adder i.e., Ripple Carry Adder using the mentor graphics tool in 90 nm CMOS technology are presented in this paper. Our experimental results show that there is 17%-70% savings in power dissipation, 4%-32% saving in the area, and 19%-84% savings in time due to approximate adder. As the LOA-2 and LOA-3 are performing optimally these two adders can be used for error-tolerant applications and based on the requirement LOA-2 or LOA-3 can be selected.

scholarly journals Modified Low Power Binary to Excess Code Converter

2015 ◽  
Vol 4 (03) ◽  
pp. 06-10
Author(s):  
Ms. Mayuri Ingole
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
Major Aspect ◽  
Code Converter ◽  
Ripple Carry Adder ◽  
Carry Select Adder ◽  
The One

Utilization of power is a major aspect in the design of integrated circuits. Since, adders are mostly employed in these circuits, we should design them effectively. Here, we propose an easy and effective method in decreasing the maximum consumption of power. Carry Select Adder is the one which is dependent on the design of two adders. We present a high performance low-power adder that is implemented. Also, here in Carry Select Adder, Binary Excess Code-1is replaced by Ripple Carry Adder. After analyzing the results, we can come to a conclusion that the architecture which is proposed will have better results in terms of consumption of power compared to conventional techniques. 

scholarly journals Sense Amplifier Half Buffer Based Ripple Carry Adder for IEEE 754 Standards

2020 ◽  
Vol 9 (3) ◽  
pp. 854-858
Keyword(s):  
Power Dissipation ◽  
Logic Design ◽  
Sense Amplifier ◽  
Ripple Carry Adder ◽  
Null Convention Logic ◽  
Systems And Control ◽  
Prime Objective ◽  
Minimum Delay ◽  
And Control ◽  
Standard Library

Addition is a specifically used indispensable computation used for most of the applications including digital systems and control systems. Adder is a primitive constituent used in the construction of digital IC; also it is an essential part of signal processing applications like DSP. The speed of an adder circuit holds a considerable influence on the total performance of digital circuits. The prime objective of this research is to design ripple carry adder using different asynchronous logics like Multithreshold null convention logic (MTNCL), Multi-threshold dual spacer dual rail delay insensitive logic (MTD3L) and proposed Sense amplifier half buffer logic (SAHB). SAHB is an asynchronous Quasi-Delay -Insensitive (QDI) method used to achieve significant functional speed of the circuit. The standard library cells (2-input AND/NAND, 2-input OR/NOR, 2-input XOR/XNOR) are designed using proposed SAHB logic to design an 8- bit Ripple Carry Adder circuit. The proposed SAHB logic design provides the solution of minimum delay with improved speed compared to the existing logic design techniques. The asynchronous logics are designed using mentor graphics tool with 130nm technology. Various performances attributes like power dissipation, delay and energy are tabulated and compared with existing logics

FBMC OQAM: novel variant of OFDM

2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Shiv Om Tiwari ◽  
Rajeev Paulus
Keyword(s):  
Orthogonal Frequency Division Multiplexing ◽  
Data Transfer ◽  
Average Power ◽  
Hybrid Technique ◽  
Filter Bank Multicarrier ◽  
Novel Variant ◽  
Good Technique ◽  
Pass Through ◽  
Papr Performance ◽  
Better Than

Abstract Orthogonal frequency division multiplexing (OFDM) revolutionizes the transmission technologies, including, optical as well as wireless communication. In OFDM the orthogonal nature of carriers makes it very good technique for data transfer. Still the out-of-band (OOB) radiation in OFDM leads to inter symbol interference (ISI) and bit error rate (BER) goes down. Moreover amplitude variations of the subcarriers lead to power variations and peak-to-average power ratio (PAPR) problem. To overcome these issues a novel filter bank multicarrier (FBMC) scheme is proposed, where each carrier is allowed to pass through to a separate filter and orthogonality among subcarriers is relaxed. Thus FBMC has better OOB and PAPR performance. In this work, we also have evaluated the PAPR performance by the simulation results. For the improvement of PAPR nonlinear companding scheme along with clipping is presented. The hybrid technique (clipping + companding) parameters are set in such a way that PAPR is reduced while signal power remains constant. Results are also compared with recent methods and it has been found that the proposed technique preforms better than other chosen techniques.

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