Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier

2015 ◽  
Vol 16 (8) ◽  
pp. 700-706 ◽  
Author(s):  
Shou-biao Tan ◽  
Wen-juan Lu ◽  
Chun-yu Peng ◽  
Zheng-ping Li ◽  
You-wu Tao ◽  
...  
Keyword(s):  
Low Voltage ◽  
Process Variation ◽  
Sense Amplifier ◽  
Multi Stage

scholarly journals An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing

2014 ◽  
Vol 11 (3) ◽  
pp. 20130992-20130992 ◽  
Author(s):  
Yi Li ◽  
Liang Wen ◽  
Yuejun Zhang ◽  
Xu Cheng ◽  
Jun Han ◽  
...  
Keyword(s):  
Low Voltage ◽  
Process Variation ◽  
Sense Amplifier ◽  
Area Efficient

A high-performance very low-voltage current sense amplifier for nonvolatile memories

2005 ◽  
Vol 40 (2) ◽  
pp. 507-514 ◽  
Author(s):  
A. Conte ◽  
G.L. Giudice ◽  
G. Palumbo ◽  
A. Signorello
Keyword(s):  
High Performance ◽  
Low Voltage ◽  
Sense Amplifier ◽  
Nonvolatile Memories

A 0.38-V operating STT-MRAM with process variation tolerant sense amplifier

2013 ◽  
Author(s):  
Yohei Umeki ◽  
Koji Yanagida ◽  
Shusuke Yoshimoto ◽  
Shintaro Izumi ◽  
Masahiko Yoshimoto ◽  
...  
Keyword(s):  
Process Variation ◽  
Sense Amplifier
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