scholarly journals Observations concerning PFD/CP operating point offset strategies for combatting static charge pump mismatch in fractional-N frequency synthesizers with digital delta-sigma modulators

2014 ◽  
Vol 5 (3) ◽  
pp. 349-364 ◽  
Author(s):  
Michael Peter Kennedy ◽  
Vahideh Sedat Sadeghi
Keyword(s):  
Charge Pump ◽  
Frequency Synthesizers ◽  
Operating Point ◽  
Static Charge ◽  
Delta Sigma

High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator

2017 ◽  
Vol E100.C (6) ◽  
pp. 548-559
Author(s):  
Anugerah FIRDAUZI ◽  
Zule XU ◽  
Masaya MIYAHARA ◽  
Akira MATSUZAWA
Keyword(s):  
High Resolution ◽  
Charge Pump ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Delta Sigma

A novel structure of dithered nested digital delta sigma modulator with low-complexity low-spur for fractional frequency synthesizers

2016 ◽  
Vol 35 (1) ◽  
pp. 157-171 ◽  
Author(s):  
Seyed Ali Sadat Noori ◽  
Ebrahim Farshidi ◽  
Sirus Sadoughi
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Synthesizers ◽  
Linear Feedback ◽  
Hardware Complexity ◽  
Order Error ◽  
Content Type ◽  
First Order ◽  
Fractional Frequency ◽  
Delta Sigma Modulator ◽  
Delta Sigma

Purpose – Digital Delta Sigma Modulator (DDSM) is used widely in electronic circuits including Radars, class-D power amplifiers and fractional frequency synthesizers. The purpose of this paper is to propose an implementation for MASH DDSMs named as Multi Modulus Reduced Complexity (MMRC) architecture. Design/methodology/approach – This architecture will use a very simple pseudorandom Linear Feedback Shift Register (LFSR) dither signal with period N_d to randomize the digital MMRC modulator used for fractional frequency synthesizers. Using error masking methodology, the MMRC modulator can decrease the hardware consumption and increase accuracy of the fractional frequency synthesizer. Rules for selecting the appropriate word lengths of the constituent MMRC modulator are derived. Findings – This paper contains three modulators. The first stage modulator is a variable modulus First Order Error Feedback Modulator and has a programmable modulus M1 that is not a power of two. The second and third stage modulators are the first order pseudorandom LFSR dithered MASH 1-1 and modified MASH 1-1-1, which have conventional modulo M2, M3, respectively. With optimum selection modulus M1, the new structure can synthesize the desired frequency exactly. Simulation results confirm the theoretical predictions. Also the results of circuit implementation proposed method reports 13 per cent reduction in hardware. Originality/value – This paper for the first time proposes a nested sigma delta modulator with a pseudorandom shaped dither signal which reduced hardware complexity and increased the period of output signal. This modulator is exploited in the fractional frequency synthesizer to the output frequency can be set more accurately.

Delta-sigma (ΔΣ) frequency synthesizers for wireless applications

2007 ◽  
Vol 29 (1) ◽  
pp. 19-30
Author(s):  
Bertan Bakkaloglu ◽  
Sayfe Kiaei ◽  
Bikram Chaudhuri
Keyword(s):  
Frequency Synthesizers ◽  
Wireless Applications ◽  
Delta Sigma
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