High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator

2017 ◽  
Vol E100.C (6) ◽  
pp. 548-559
Author(s):  
Anugerah FIRDAUZI ◽  
Zule XU ◽  
Masaya MIYAHARA ◽  
Akira MATSUZAWA
Keyword(s):  
High Resolution ◽  
Charge Pump ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Delta Sigma

FPGA Based High Resolution Time to Digital Converter

2011 ◽  
pp. 127-146 ◽  
Author(s):  
Rajanish K. Kamat ◽  
Santosh A. Shinde ◽  
Pawan K. Gaikwad ◽  
Hansraj Guhilot
Keyword(s):  
High Resolution ◽  
Digital Converter ◽  
Resolution Time ◽  
Time To Digital Converter

A High-Resolution and Low Offset Delta-Sigma Analog to Digital Converter for Detecting Photoplethysmography Signal

2021 ◽  
Author(s):  
Eka Fitrah Pribadi ◽  
Rajeev Kumar Pandey ◽  
Paul C.-P. Chao
Keyword(s):  
High Resolution ◽  
Continuous Time ◽  
Operational Amplifier ◽  
High Frequency ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Low Offset

Abstract A high-resolution, low offset delta-sigma analog to digital converter for detecting photoplethysmography (PPG) signal is presented in this study. The PPG signal is a bio-optical signal incorporated with heart functionality and located in the range of 0.1–10 Hz. The location to get PPG signal is on a pulsating artery. Thus the delta-sigma analog-to-digital (DS ADC) converter is designed specifically in that range. However, the DS ADC circuitry suffers from 1/f noise under 10 Hz frequency range. A chopper based operational amplifier is implemented in DS ADC to push the 1/f noise into high-frequency noise. The dc offset of the operational amplifier is also pushed to the high-frequency region. The DS ADC circuitry consists of a second-order continuous-time delta-sigma modulator. The delta-sigma modulator circuitry is designed and simulated using TSMC 180 nm technology. The continuous-time delta-sigma modulator active area layout is 746μm × 399 μm and fabricated using TSMC 180 nm technology. It operates in 100 Hz bandwidth and 4096 over-sampling ratios. The SFDR of the circuit is above 70 dB. The power consumption of the delta-sigma modulator is 35.61μW. The simulation is performed in three different kinds of corner, SS, TT, and FF corner, to guarantee the circuitry works in different conditions.

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