The Two-Step Growth Mechanism of MOCVD GaAs/Si

1987 ◽  
Vol 91 ◽  
Author(s):  
Koichi Ishida
Keyword(s):  
Buffer Layer ◽  
Growth Mechanism ◽  
Growth Temperature ◽  
Direct Consequence ◽  
Gaas Layer ◽  
Misfit Dislocations ◽  
Misfit Stress ◽  
Mocvd Growth ◽  
Transmission Electron ◽  
Stress Free State

AbstractThe growth mechanism and lattice defects are studied for GaAs/Si grown by the two-step MOCVD growth procedure using transmission electron microscopy (TEM). The large misfit stress between GaAs and Si is relieved by misfit dislocations at the GaAs/Si interface, which are introduced during epitaxial regrowth of the thin (<200A) polycrystalline buffer layer grown at 400∼450°C. The regrown buffer layer is relaxed to a nearly stress free state, and therefore a thick GaAs layer can subsequently be grown at the higher growth temperature (∼750°C). The tensile stress in GaAs at room temperature is shown to be a direct consequence of the misfit stress relaxation at the higher growth temperature. TEM revealed high density (<106cm−2) of the threading dislocations in the GaAs layer, contrary to the results of molten KOH etching.

MBE Growth of Low Dislocation and High Mobility GaAs-on-Si

1986 ◽  
Vol 67 ◽  
Author(s):  
Jhang Woo Lee
Keyword(s):  
Layer Structure ◽  
High Mobility ◽  
Gaas Layer ◽  
Buffer Layers ◽  
Misfit Dislocations ◽  
Si Substrates ◽  
Molecular Beam Epitaxial ◽  
Transmission Electron ◽  
Low Dislocation Density ◽  
Molecular Beam Epitaxial Growth

ABSTRACTData is presented on the optimization of several molecular beam epitaxial growth processes to provide low dislocation density and high mobility GaAs single crystals on (100) Si wafers. The substrate tilt angle, the growth temperature, and the first buffer layer structure, were investigated Tor this purpose. Using Hall measurements the GaAs layers grown on 2 or 3-degree tilt (100) Si showed consistently high mobilities which are equivalent to the homoepitaxial GaAs mobility. Transmission electron microscopy (TEM) revealed that on tilted (100) Si substrates most of the misfit dislocations were confined within the first 50 Å GaAs layer by forming a type of edge dislocation at the Si surface step edges. Also low temperature grown buffer layers always gave better morphologies and lower etch pit densities while keeping the high mobilities on overgrown GaAs layers.

Growth and Characterizations of Gaas on Inp with Different Buffer Structures by Molecular Beam Epitaxy

1989 ◽  
Vol 148 ◽  
Author(s):  
Xiaoming Liu ◽  
Henry P. Lee ◽  
Shyh Wang ◽  
Thomas George ◽  
Eicke R. Weber ◽  
...  
Keyword(s):  
Low Temperature ◽  
Buffer Layer ◽  
Gaas Layer ◽  
Optical Quality ◽  
Cross Sectional ◽  
Transmission Electron ◽  
Layer Structures ◽  
Gaas Films ◽  
Initial Deposition ◽  
Strained Layer Superlattices

ABSTRACTWe report the growth and characterizations of 31μm thick GaAs films grown on (100) InP substrates by MBE employing different buffer layer structures during the initial deposition. The buffer layer structures under study are: 1) GaAs layer grown at low temperature; 2) GaAs layer grown at low temperature plus two sets of In0.08Ga0.92As/GaAs strained layer superlattices (SLS) and 3) a transitional compositionally graded InxGal-xAs layer between the InP substrate and the GaAs film. After the buffer layer deposition, the growth was continued by conventionalMBE to a total thickness of 3μm for all samples. From the 77K photoluminescence (PL) measurement, it was found that the sample with SLS layers has the highest PL intensity and the narrowest PL linewidth. Cross-sectional transmission electron microscopy (TEM) studies showed that the SLS is effective in reducing the propagation of threading dislocations and explains the observed superior optical quality from the PL measurement.

scholarly journals The Structure of GaAs/Si(211) Heteroepitaxial Layers

1987 ◽  
Vol 91 ◽  
Author(s):  
Zuzanna Liliental-Weber ◽  
E.R. Weber ◽  
J. Washburn ◽  
T.Y. Liu ◽  
H. Kroemer
Keyword(s):  
Buffer Layer ◽  
Surface Preparation ◽  
Gaas Layer ◽  
Misfit Dislocations ◽  
Strained Layer ◽  
Si Substrates ◽  
Density Of Dislocations ◽  
Gaas Buffer Layer ◽  
Graded Layers ◽  
Strained Layer Superlattices

ABSTRACTGallium arsenide films grown on (211)Si by molecular-beam epitaxy have been investigated using transmission electron microscopy. The main defects observed in the alloy were of misfit dislocations, stacking faults, and microtwin lamellas. Silicon surface preparation was found to play an important role on the density of defects formed at the Si/GaAs interface.Two different types of strained-layer superlattices, InGaAs/InGaP and InGaAs/GaAs, were applied either directly to the Si substrate, to a graded layer (GaP-InGaP), or to a GaAs buffer layer to stop the defect propagation into the GaAs films. Applying InGaAs/GaAs instead of InGaAs/InGaP was found to be more effective in blocking defect propagation. In all cases of strained-layer superlattices investigated, dislocation propagation was stopped primarily at the top interface between the superlattice package and GaAs. Graded layers and unstrained AlGaAs/GaAs superlattices did not significantly block dislocations propagating from the interface with Si. Growing of a 50 nm GaAs buffer layer at 505°C followed by 10 strained-layer superlattices of InGaAs/GaAs (5 nm each) resulted in the lowest dislocation density in the GaAs layer (∼;5×l07/cm2) among the structures investigated. This value is comparable to the recently reported density of dislocations in the GaAs layers grown on (100)Si substrates [8]. Applying three sets of the same strained layersdecreased the density of dislocations an additional ∼2/3 times.

Tem Assessment of Defects in (CdHg)Te Heterostructures

1990 ◽  
Vol 216 ◽  
Author(s):  
S.G. Lawson-Jack ◽  
I.P. Jones ◽  
D.J. Williams ◽  
M.G. Astles
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Buffer Layer ◽  
High Density ◽  
Misfit Dislocations ◽  
Cross Sectional ◽  
Burgers Vector ◽  
Density Of Dislocations ◽  
Transmission Electron ◽  
Interfacial Plane

ABSTRACTTransmission electron microscopy has been used to assess the defect contents of the various layers and interfaces in (CdHg) Te heterostructures. Examination of cross sectional specimens of these materials suggests that the density of misfit dislocations at the interfaces is related to the layer thicknesses, and that the high density of dislocations which are generated at the GaAs/CdTe interface are effectively prevented from penetrating into the CdHgTe epilayer by a 3um thick buffer layer. The majority of the dislocations in the layers were found to have a Burgers vector b = a/2<110> and either lie approximately parallel or inclined at an angle of ∼ 60° to the interfacial plane.

Liquid Phase Epitaxial Growth and Characterization of GaAs on InP Substrates

1994 ◽  
Vol 340 ◽  
Author(s):  
Dong-Keun Kim ◽  
Hyung-Jong Lee ◽  
Byung-Teak Lee
Keyword(s):  
Liquid Phase ◽  
Surface Morphology ◽  
Growth Conditions ◽  
Gaas Layer ◽  
Misfit Dislocations ◽  
Double Crystal ◽  
Transmission Electron ◽  
Grating Region ◽  
Inp Substrates ◽  
Undoped Gaas

ABSTRACTOptimum growth conditions were investigated to obtain high quality heteroepitaxial GaAs layers on InP substrates by liquid phase epitaxy (LPE). Addition of about 0.005wt% of Se to the Ga growth melt effectively suppressed dissolution of the InP substrates into the melt during the initial stage of the growth, resulting in a significantly improved surface morphology. The crystallinity and the surface morphology could be further improved by growing undoped GaAs layers on thin Se-doped buffer GaAs as well as using InP substrates patterned with grating structure. The transmission electron microscopy observation indicated that the misfit dislocations interact with each other at the grating region, resulting in a lower dislocation density in the upper GaAs layer. The (400) double crystal X-ray diffraction peaks of the undoped GaAs showed fullwidth- at-half-maximum of about 380 arcsec, which is comparable with the previously reported values using more sophisticated growth techniques.

A Study of FeAl/AlAs/GaAs Interfaces Using Moiré-Fringe Contrast in a Transmission Electron Microscope

1990 ◽  
Vol 202 ◽  
Author(s):  
J. E. Angelo ◽  
J.N. Kuznia ◽  
A.M. Wowchak ◽  
P. I. Cohen ◽  
W. W. Gerberich
Keyword(s):  
Electron Microscope ◽  
Transmission Electron Microscope ◽  
Growth Temperature ◽  
Growth Mode ◽  
Misfit Dislocations ◽  
Layer By Layer ◽  
Plan View ◽  
Transmission Electron ◽  
Moire Fringe ◽  
Moiré Fringe

ABSTRACTThis paper describes the transmission electron microscope (TEM) investigations of the defect structure present at various FeAl/AlAs/GaAs interfaces. Although a systematic study has not yet been completed it is shown that by changing the growth temperature from 200°C to 300°C the growth morphology changes significantly. In-situ RHEED studies show the growth mode changes from layer-by-layer to island-like when the growth temperature is increased. TEM in both plan-view and cross-sectional modes is used to confirm these results. It is found that by increasing the growth temperature from 200°C to 300°C the growth mode switches from layer-by-layer (2D) with a continuous FeAl film, to island-like (3D) with significant numbers of “pin-holes”. A Moiré-fringe analysis is applied to determine the Burgers vector of the misfit dislocations. In both cases the interface between the FeAl and AlAs consists of a grid of misfit dislocations with [100] and [010] line directions whose Burgers vectors are [010] and [100] respectively.

Mocvd Growth of GaAs on Si

1988 ◽  
Vol 116 ◽  
Author(s):  
Masahiro Akiyama ◽  
Takash Ueda ◽  
Sachiko Onozawa
Keyword(s):  
High Temperatures ◽  
Growth Temperature ◽  
Room Temperature ◽  
Gaas Layer ◽  
Grown Layer ◽  
Gaas On Si ◽  
Mocvd Growth ◽  
Initial Stage ◽  
Step Growth ◽  
Domain Property

AbstractThe initial stage of the growth of GaAs on Si by, MOCVD, the reduction of the residual dislocations by annealing at high temperatures and the dependence of the growth temperature on the stress in the GaAs layer were studied. The density and the size of deposited GaAs islands at the initial stage of the growth in the two-step growth sequence strongly affected the domain property of the subsequently grown layer. For reducing the residual dislocations by annealing at high temperatures, to repeat the growth and the annealing was more effective method compared with the other annealing methods we tried. The stress in the GaAs layers showed a constant value independently of the growth temperature and the value was related to the thermal expansion between room temperature and about 350°C.

Characterization of ErAs/GaAs and GaAs/ErAs/GaAs Structures

1989 ◽  
Vol 160 ◽  
Author(s):  
Jane G. Zhu ◽  
Chris J. Palmstrøm ◽  
Suzanne Mounier ◽  
C. Barry Carter
Keyword(s):  
Electron Microscopy ◽  
High Resolution Electron Microscopy ◽  
Gaas Layer ◽  
Misfit Dislocations ◽  
Weak Beam ◽  
Transmission Electron ◽  
Resolution Electron ◽  
Small Grains ◽  
Major Defect

AbstractA series of ErAs/GaAs and GaAs/ErAs/GaAs epilayers have been grown on (100) GaAs substrates by molecular-beam epitaxy. Misfit dislocations at the ErAs/GaAs interface have been analyzed using the weak-beam technique of transmission electron microscopy. The microstructure of GaAs/ErAs/GaAs layers have been characterized using conventional and high-resolution electron microscopy. Twinning inside the upper GaAs layer is the major defect. Although the desired epitactic (100) GaAs on (100) ErAs does dominate, small grains of GaAs with (111) or {122} orientations have been observed at the GaAs/ErAs heterojunction.

Anisotropy of Strain Relaxation in III-V Semiconductor Heterostructures

2004 ◽  
Vol 230-232 ◽  
pp. 93-100 ◽  
Author(s):  
O. Yastrubchak ◽  
T. Wosiński ◽  
J.Z. Domagała ◽  
E. Łusakowska
Keyword(s):  
Lattice Mismatch ◽  
Strain Relaxation ◽  
Growth Conditions ◽  
Threading Dislocation ◽  
Misfit Dislocations ◽  
Misfit Stress ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron ◽  
Small Lattice

Partially relaxed III–V heterostructures: GaAs/InGaAs and InP/InAlAs/InGaAs, with a small lattice mismatch, grown using molecular beam epitaxy under compressive or tensile misfit stress at the (001) interface, have been investigated by means of high-resolution X-ray diffractometry, atomic force microscopy and generalized ellipsometry. Additionally, transmission electron microscopy and electron-beam induced current in a scanning electron microscope have been employed to reveal misfit dislocations at the heterostructure interface. Chemical etching was used to determine polarity of the crystals and threading dislocation densities in the epitaxial layers. Our findings are interpreted in terms of the dependent on growth conditions, material’s composition and doping glide velocities of two types of misfit dislocations: α and β, differing in their core structure and lying along two orthogonal 〈110〉 crystallographic directions at the (001) interface.

In situ TEM measurements of the electrical properties of interface dislocations

1992 ◽  
Vol 50 (2) ◽  
pp. 1338-1339
Author(s):  
F. M. Ross ◽  
R. Hull ◽  
D. Bahnck ◽  
J. C. Bean ◽  
L. J. Peticolas ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Electronic Device ◽  
In Situ Tem ◽  
Device Performance ◽  
Misfit Dislocations ◽  
Electrical Characteristics ◽  
Strained Layer ◽  
Transmission Electron ◽  
Interfacial Dislocations

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.

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