Fabrication of Strained Silicon on Insulator (SSOI) by Direct Wafer Bonding Using Thin Relaxed SiGe Film as Virtual Substrate

2004 ◽  
Vol 809 ◽  
Author(s):  
J.J. Lee ◽  
J.S. Maa ◽  
D. J. Tweet ◽  
S.T. Hsu
Keyword(s):  
Wafer Bonding ◽  
Lattice Relaxation ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Si Substrate ◽  
Strained Si ◽  
Drive Current ◽  
Defect Zone ◽  
Direct Wafer Bonding ◽  
Strained Sige

ABSTRACTNMOS devices have been successfully fabricated on SSOI wafers. The SSOI wafer fabrication is by direct wafer bonding and wafer transfer by splitting of the strained Si on thin SiGe virtual substrate to an oxidized wafer. The thin SiGe virtual substrate is fabricated by strained SiGe deposition, H2+ implantation, and SiGe lattice relaxation anneal. This relaxation process creates a confined defect zone at the SiGe to Si substrate interface that ensures low defect strained Si growth. 10 μm by 10 μm NMOS SSOI devices show an improvement of 100% in drive current and 115% in transconductance. A near ideal subthreshold swing was observed on NMOS devices with channel length as short as 0.1 μm.

A Comparative Study for the Backside Illumination (BSI) Technology Using Bonding Wafer Cleaning Process for Advanced CMOS Image Sensor

2012 ◽  
Vol 195 ◽  
pp. 75-78
Author(s):  
Chung Kyung Jung ◽  
Sung Wook Joo ◽  
Seoung Hun Jeong ◽  
Sang Wook Ryu ◽  
Han Choon Lee ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Comparative Study ◽  
Quantum Efficiency ◽  
Wafer Bonding ◽  
Image Sensor ◽  
Silicon On Insulator ◽  
Cleaning Process ◽  
Electrochemical Systems ◽  
Wafer Cleaning ◽  
Direct Wafer Bonding

Over the last decades, the concept of backside illumination (BSI) sensors has become one of the leading solutions to optical challenges such as improved quantum efficiency (QE), and cross-talk, respectively [1-. Direct wafer bonding is a method for fabricating advanced substrates for micro-electrochemical systems (MEMS) and integrated circuits (IC). The most typical example of such an advanced substrate is the silicon-on-insulator (SOI) wafer.

Structural Evaluation of Silicon‐on‐Insulator Fabricated by a Direct Wafer Bonding and Numerically Controlled Polishing Technique

1991 ◽  
Vol 138 (8) ◽  
pp. 2468-2474 ◽  
Author(s):  
A. Yamada ◽  
Bai‐Lin Jiang ◽  
G. A. Rozgonyi ◽  
H. Shirotori ◽  
O. Okabayashi ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Silicon On Insulator ◽  
Structural Evaluation ◽  
Direct Wafer Bonding

Relaxation of Strained SiGe on Insulator by Direct Wafer Bonding

2004 ◽  
Vol 809 ◽  
Author(s):  
Jer-shen Maa ◽  
Jong-Jan Lee ◽  
Douglas Tweet ◽  
Sheng Teng Hsu
Keyword(s):  
Silicon Dioxide ◽  
Wafer Bonding ◽  
Annealing Temperature ◽  
Relaxation Mechanism ◽  
Film Structure ◽  
Oxide Surface ◽  
Direct Wafer Bonding ◽  
High Degree ◽  
Possible Cause ◽  
Strained Sige

ABSTRACTStrained SiGe was bonded to silicon dioxide by direct wafer bonding and Smart-cut technique. Strained SiGe with a graded 20%-30% Ge concentration was deposited by RTCVD on (100) Si to a thickness between 300nm to 350nm. H2+ for wafer splitting was implanted at an energy varied from 40 keV to 150 keV and a dose between 2.5E16 and 4.5E16 ions/cm2. SiGe relaxation was found to depend on wafer split temperature, and on post-split annealing temperature. SiGe relaxation of greater than 80% was observed after wafer splitting and annealing. Was it from gliding of a SiGe film weakly bonded to an oxide surface? In order to determine the relaxation mechanism, samples with different film structure were prepared. The films were then annealed at various temperatures. Some film showed a high degree of relaxation, and some showed minimal relaxation, depending mostly on hydrogen implant depth. The results indicated that the generation of dislocation is the possible cause of SiGe relaxation.

Seebeck Coefficient of Ge-on-Insulator Layers Fabricated by Direct Wafer Bonding Process

2015 ◽  
Vol 1117 ◽  
pp. 94-97 ◽  
Author(s):  
Veerappan Manimuthu ◽  
Shoma Yoshida ◽  
Yuhei Suzuki ◽  
Faiz Salleh ◽  
Mukannan Arivanandhan ◽  
...  
Keyword(s):  
Seebeck Coefficient ◽  
Wafer Bonding ◽  
Annealing Effect ◽  
Bonding Process ◽  
Infrared Photodetector ◽  
Si Substrate ◽  
Temperature Range ◽  
Direct Wafer Bonding ◽  
Insulator Layers ◽  
P Type

We investigate thermoelectric characteristics of SiGe nanostructures for realizing high-sensitive infrared photodetector applications. In this paper, for future Ge and SiGe nanowires, we fabricate p-type Ge-on-insulator (GOI) substrates by a direct wafer bonding process. We discuss the annealing effect on the GOI substrate in the process and measure its Seebeck coefficient in the temperature range of 290-350 K. The Seebeck coefficient of the GOI layers is almost identical with the reported values for Ge. This result confirms that the measured Seebeck coefficient of GOI layers is not influenced by the buried oxide (BOX) layer and the Si substrate.

Silicon on insulator optical waveguides formed by direct wafer bonding

1992 ◽  
Vol 15 (2) ◽  
pp. 156-159 ◽  
Author(s):  
G.T. Reed ◽  
Li Jinhua ◽  
C.K. Tang ◽  
Lin Chenglu ◽  
P.L.F. Hemment ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Optical Waveguides ◽  
Silicon On Insulator ◽  
Direct Wafer Bonding

TEM Study of bonded silicon wafers

1995 ◽  
Vol 53 ◽  
pp. 460-461
Author(s):  
L. Mulestagno ◽  
R. Craven ◽  
P. Fraundorf
Keyword(s):  
Wafer Bonding ◽  
Silicon Film ◽  
Poor Quality ◽  
Silicon On Insulator ◽  
Back Side ◽  
Interface Quality ◽  
Direct Wafer Bonding ◽  
Analytical Work ◽  
Radiation Hard ◽  
Plane View

The promise of higher speed, radiation hard, high temperature capabilities, and increased device density has made SOI ( silicon - on - insulator) an attractive proposition since its conception several years ago . Until recently the methods for its manufacture had been plagued by low yields, and poor quality . Remarkable advances have been made lately resulting in increasing quantities of SOI wafers being sold commercially.The two main techniques for making SOI are Separation by Implantation of Oxygen (SIMOX) and direct wafer bonding (Bonded wafers). Little analytical work has yet been performed on the latter by the microscopy community at large, so we studied 2 commercial quality wafers with the intent of looking for particulate defects which might arise during annealing, and studying the oxide layer and oxide-SOI interface quality.Plane view samples were made from the SOI taking advantage of its chemistry, by dimpling and milling from the back-side, and then dipping in HF which attacks the oxide, and leaves large areas of silicon film suitable for TEM untouched.

GaAs solar cell on Si substrate with good ohmic GaAs/Si interface by direct wafer bonding

2015 ◽  
Vol 141 ◽  
pp. 372-376 ◽  
Author(s):  
SangHyeon Kim ◽  
Dae-Myeong Geum ◽  
Min-Su Park ◽  
Chang Zoo Kim ◽  
Won Jun Choi
Keyword(s):  
Solar Cell ◽  
Wafer Bonding ◽  
Si Substrate ◽  
Direct Wafer Bonding
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