Silver Damascene Process with Cap Layer

2002 ◽  
Vol 732 ◽  
Author(s):  
Masahiro Ota ◽  
Manabu Tsujimura ◽  
Hiroaki Inoue ◽  
Hirokazu Ezawa ◽  
Masahiro Miyata
Keyword(s):  
Dielectric Constant ◽  
Noble Metals ◽  
Effective Dielectric Constant ◽  
New Materials ◽  
Technology Roadmap ◽  
Cap Layer ◽  
Planarization Process ◽  
High K Materials ◽  
Cu Interconnect ◽  
Low K

AbstractDevelopment of semiconductors has proceeded according to broad frameworks such as the International Technology Roadmap for Semiconductors (ITRS). A key development in semiconductor technology involves the adoption of several new materials, such as Cu, low-k and high-k materials, and noble metals in capacitors, transistors, and/or interconnects. These developments will likely lead to wider application of the planarization process to new processes and new materials, and call for even stricter planarization performance requirements. One example involves planarizing Ag interconnects with an optimal cap layer configuration for reducing RC delays. The Cu interconnect process is currently used to reduce wire resistivity. One material that has been proposed as a successor to Cu is Ag. Many low-k materials have been developed with the goal of reducing dielectric constant (k). However, damascene design and matters such as cap layer configuration are also important considerations in reducing the effective dielectric constant (k eff). Our report herein begins by proposing Ni-B deposited by electroless plating as a candidate cap material, due to the following characteristics: (1) it offers good selectivity for Ag interconnects; (2) it provides good barrier effects through thermal processes; and (3) it provides good controllability of deposition rates. Next, we report that Ag damascene with Ni-B cap layer can be realized through electroplating and polishing of Ag interconnects. Although Ag polishing technologies are currently not fully developed, we suggest that they may nevertheless be successfully applied to polish Ag.

Slurry Development For Cu/Ultra Low k CMP

2003 ◽  
Vol 767 ◽  
Author(s):  
Hugh Li ◽  
Matt VanHaneham ◽  
John Quanci
Keyword(s):  
Dielectric Constant ◽  
Mechanical Strength ◽  
Chemical Reactions ◽  
Relative Velocity ◽  
Planarization Process ◽  
Technical Challenges ◽  
Low K

Conventional CMP for Cu/Ultra-low k (k<2.4) integration faces significant technical challenges [1-2]. The majority of ULK materials are made porous to reduce the dielectric constant, while trading off on the mechanical strength [3-6]. With diminished hardness, elasticity and adhesion, the CMP process has to be “kinder and gentler”: lower down force, lower relative velocity, softer pad, and slurry with lower abrasive content [1,7]. In a word, the mechanical portion of the planarization process would be greatly reduced. To maintain the same performance, one has to rely on the chemical reactions to make Cu/ULK CMP a viable process.

Integration of a Polymer Etch Stop Layer in a Porous Low K MLM Structure

2005 ◽  
Vol 863 ◽  
Author(s):  
Gregory C. Smith ◽  
Neil Henis ◽  
Richard McGowan ◽  
Brian White ◽  
Matthias Kraatz ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Dielectric Constant ◽  
Effective Dielectric Constant ◽  
Metal Structures ◽  
Etch Stop ◽  
Etch Stop Layer ◽  
Low K

AbstractTwo level metal structures were fabricated to test the efficacy of using an organic low K etch stop layer (OESL) in order to lower the effective dielectric constant for intralayer capacitance. The organic etch stop layer's intrinsic capacitance of 3.3 compares with that of silicon carbide (∼ 5) which constitutes the control of the experiment. This reduction represents a reduction of effective dielectric constant for the stack of about 10% to about 3.0. The process was optimized so as to achieve yield of via chains of a million 130 nm diameter vias, and effective K was measured. The target of 3.0 was achieved using this process. Interpenetration of the organic etch stop with the MSQ porous low K material was observed.

Passivation Cracks in a Four-Level Metal Low-K Dielectric Backend Process

2000 ◽  
Author(s):  
Michael C. Olewine ◽  
John F. DiGregorio ◽  
Gus J. Colovos ◽  
Kevin F. Saiz ◽  
Hongjiang Sun
Keyword(s):  
Integrated Circuit ◽  
Chemical Vapor ◽  
Low Dielectric Constant ◽  
New Materials ◽  
Hydrogen Silsesquioxane ◽  
Low Dielectric ◽  
Passivation Layers ◽  
Cu Interconnect ◽  
First Time ◽  
Low K

Abstract Mechanical stress problems in integrated circuit devices are becoming more severe as the number of metal interconnect levels increases and new materials such as low-k dielectrics are introduced. We studied dielectric cracking in a four-level Al-Cu interconnect structure that uses hydrogen silsesquioxane (HSQ), a low dielectric constant (low-k) material. The cracks extended down through the passivation layers to the HSQ layer. For the first time we report on passivation dielectric cracks directly related to the level of residual fluorine in a plasma enhanced chemical vapor deposition (PECVD) reactor. It is shown that a silicon nitride pre-coat deposition removes fluorine (F) from the reactor ambient and prevents the dielectric cracks.

Low-Dielectric Constant SiO(F,C) Films for ULSI Interconnections Prepared by CF4 Plasma Ion Implantation

1998 ◽  
Vol 511 ◽  
Author(s):  
Yuanzhong Zhou ◽  
Shu Qin ◽  
Chung Chan ◽  
Paul K. Chu
Keyword(s):  
Dielectric Constant ◽  
Ion Implantation ◽  
Breakdown Strength ◽  
Plasma Reactor ◽  
Effective Dielectric Constant ◽  
Electrical Field ◽  
Low Dielectric ◽  
Double Layer Model ◽  
Doping Technique ◽  
Low K

ABSTRACTPlasma ion implantation (PII) doping technique has been utilized to prepare a new lowdielectric constant (low k) material SiO(F,C). Fluorine and carbon were implanted into SiO2 films by CF4 PII using an ICP plasma reactor. The effective dielectric constant of the films was significantly reduced after PH doping. An analysis of a double layer model indicated that a high quality dielectric layer with a dielectric constant down to 2.8 can be achieved by an optimized PII process. Contrasting to other conventional low-k material techniques, PII process also improved bulk resistivity and electrical field breakdown strength. The improvement possibly resulted from adding carbon into the films. The etching effect of CF4 PII could be beneficial to planarization and gap filling of dielectric interlayer.

Preparation of Nano Structured SiOC Thin Film for Low k Application

2010 ◽  
Vol 11 ◽  
pp. 85-88 ◽  
Author(s):  
Woo Teck Kwon ◽  
J.H. Lee ◽  
Soo Ryong Kim ◽  
H.T. Kim ◽  
Hyung Sun Kim ◽  
...  
Keyword(s):  
Thin Film ◽  
Dielectric Constant ◽  
Dielectric Properties ◽  
Dip Coating ◽  
Interlayer Dielectrics ◽  
Promising Application ◽  
Cu Interconnect ◽  
Interconnect Technology ◽  
Low K ◽  
Mim Capacitors

In our study, the dielectric properties of SiOC low k thin film derived from polyphenylcarbosilane were investigated as a potential interlayer dielectrics for Cu interconnect technology. A SiOC low k thin film was fabricated onto a n-type silicon wafer by dip coating using 30wt % polyphenylcarbosilane in cyclohexane. Curing of the film was performed in air at 300°C for 2h. The thickness of the film ranges from 1 μm to 1.7 μm. The dielectric constant was determined from the capacitance data obtained from metal/polyphenylcarbosilane/conductive Si MIM capacitors and shows a dielectric constant as low as 3.26 without porosity added. The SiOC low k thin film derived from polyphenylcarbosilane shows promising application as an interlayer dielectrics for Cu interconnect technology.

0.1μm Interconnect Technology Challenges and the Sia Roadmap

1996 ◽  
Vol 427 ◽  
Author(s):  
Tom Seidel ◽  
Bin Zhao ◽  
Sematech ◽  
T X Austin
Keyword(s):  
Dielectric Constant ◽  
Thermal Management ◽  
Low Cost ◽  
Electrical Characterization ◽  
Barrier Materials ◽  
Low Dielectric ◽  
Technology Roadmap ◽  
Aspect Ratios ◽  
Lower Dielectric Constant ◽  
Low K

AbstractAnalysis of the National Technology Roadmap for Semiconductors (SIA) indicates a potential crisis in performance and reliability regarding the scaling of interconnects. In the future, increased component density and performance (e.g. logic instructions / sec.) may not be able to be achieved simultaneously for technology generations well before the manufacture of 0.1μm feature sizes circa 2005. Thermal management and engineering of signal noise are key issues. Although much can be done to achieve higher speed with product design architecture, one must consider new material paradigms by 0. 1μm generation to address the RC crisis.Needs exist in low cost simplified processes across a broad area of applications: local salicide interconnects, lower process temperature for poly-metal dielectric (to enable shallower junctions), lower dielectric constant materials for interconnects, and robust barriers for interconnect plugs and wiring metals. A shift to lower dielectric constant (low-k) materials (e.g. SiO-F, polymers, or aerogels) will be used as soon as integrated processes are demonstrated and manufacturing tools become available. The next full generation window of opportunity is the 0.18um generation (1GB) scheduled for manufacturing prototyping in 1998.This paper reviews the overall Roadmap characteristics, major solution strategies, and outlines the challenges in design, technology, and integration for 0.18μm and 0.1μm generations. Topics reviewed include discussion of process architectures and electrical characterization methodologies. Among the most challenging areas we have: control and lowering of contact resistance, manufacturing interconnects at aspect ratios exceeding 4:1, use of very low dielectric constant materials in multilevel counts approaching 6–7, use of controllable ultra thin barrier materials for interconnect plugs and wiring, barriers and cladding for containment and passivation of Cu, development of manufacturing worthy selective processes, engineering stress/electromigration issues and thermal management of low-k dielectric systems. New materials must be introduced into existing technology frameworks while designs migrate to lower voltage operation.

Structire, Properties, and Process Characteristics of Low-K Materials Prepared by PECVD

1999 ◽  
Vol 565 ◽  
Author(s):  
Y. Shimogaki ◽  
S. W. Lim ◽  
E. G. Loh ◽  
Y. Nakano ◽  
K. Tada ◽  
...  
Keyword(s):  
Growth Rate ◽  
Dielectric Constant ◽  
Gas Flow ◽  
Structural Changes ◽  
Silicon Oxide ◽  
Reactive Species ◽  
Low Dielectric Constant ◽  
Low Dielectric ◽  
Step Coverage ◽  
Low K

AbstractLow dielectric constant F-doped silicon oxide films (SiO:F) can be prepared by adding fluorine source, like as CF4 to the conventional PECVD processes. We could obtain SiO:F films with dielectric constant as low as 2.6 from the reaction mixture of SiH4/N2 O/CF4. The structural changes of the oxides were sensitively detected by Raman spectroscopy. The three-fold ring and network structure of the silicon oxides were selectively decreased by adding fluorine into the film. These structural changes contribute to the decrease ionic polarization of the film, but it was not the major factor for the low dielectric constant. The addition of fluorine was very effective to eliminate the Si-OH in the film and the disappearance of the Si-OH was the key factor to obtain low dielectric constant. A kinetic analysis of the process was also performed to investigate the reaction mechanism. We focused on the effect of gas flow rate, i.e. the residence time of the precursors in the reactor, on growth rate and step coverage of SiO:F films. It revealed that there exists two species to form SiO:F films. One is the reactive species which contributes to increase the growth rate and the other one is the less reactive species which contributes to have uniform step coverage. The same approach was made on the PECVD process to produce low-k C:F films from C2F4, and we found ionic species is the main precursor to form C:F films.

The characterization and preparation of porous low dielectric films using various cyclodextrins as template materials

2003 ◽  
Vol 766 ◽  
Author(s):  
Jin-Heong Yim ◽  
Jung-Bae Kim ◽  
Hyun-Dam Jeong ◽  
Yi-Yeoul Lyu ◽  
Sang Kook Mah ◽  
...  
Keyword(s):  
Thin Film ◽  
Mechanical Properties ◽  
Dielectric Constant ◽  
Pore Structure ◽  
Pore Diameter ◽  
Dielectric Films ◽  
Low Dielectric Constant ◽  
Cyclodextrin Derivatives ◽  
Low Dielectric ◽  
Low K

AbstractPorous low dielectric films containing nano pores (∼20Å) with low dielectric constant (<2.2), have been prepared by using various kinds of cyclodextrin derivatives as porogenic materials. The pore structure such as pore size and interconnectivity can be controlled by changing functional groups of the cyclodextrin derivatives. We found that mechanical properties of porous low-k thin film prepared with mCSSQ (modified cyclic silsesquioxane) precursor and cyclodextrin derivatives were correlated with the pore interconnection length. The longer the interconnection length of nanopores in the thin film, the worse the mechanical properties of the thin film (such as hardness and modulus) even though the pore diameter of the films were microporous (∼2nm).

Measurement of effective dielectric constant : A comparison

2011 ◽  
Author(s):  
Aakashdeep ◽  
Saurav Kr. Basu ◽  
G. V. Ujjwal ◽  
Sakshi Kumari ◽  
V. R. Gupta
Keyword(s):  
Dielectric Constant ◽  
Effective Dielectric Constant
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