Strained Ge Channel p-type MOSFETs Fabricated on Si1−xGex/Si Virtual Substrates

2001 ◽  
Vol 686 ◽  
Author(s):  
Minjoo L. Lee ◽  
Christopher W. Leitz ◽  
Zhiyuan Cheng ◽  
Arthur J. Pitera ◽  
Gianni Taraschi ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
High Mobility ◽  
Silicon Layer ◽  
Hole Mobility ◽  
Oxide Semiconductor ◽  
Epitaxial Silicon ◽  
Wide Range ◽  
Epitaxial Silicon Layer ◽  
P Type ◽  
Mos Device

AbstractWe have fabricated strained Ge channel p-type metal oxide semiconductor field-effect transistors (p-MOSFETs) on Si1−xGex (x=0.7 to 0.9) virtual substrates. Capping the channel with a relaxed, epitaxial silicon layer eliminates the poor interface between silicon dioxide (SiO2) and pure Ge. The effects of the Si cap thickness, the strain in the Ge channel, and the thickness of the Ge channel on hole mobility enhancement were investigated. Optimized strained Ge p-MOSFETs show hole mobility enhancements of nearly 8 times that of co-processed bulk Si devices across a wide range of vertical field. These devices demonstrate that the high mobility holes in strained Ge can be utilized in a MOS device despite the need to cap the channel with a highly dislocated Si layer.

Hole mobility enhancements in strained Si/Si1−yGey p-type metal-oxide-semiconductor field-effect transistors grown on relaxed Si1−xGex (x

2001 ◽  
Vol 79 (25) ◽  
pp. 4246-4248 ◽  
Author(s):  
C. W. Leitz ◽  
M. T. Currie ◽  
M. L. Lee ◽  
Z.-Y. Cheng ◽  
D. A. Antoniadis ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Hole Mobility ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Strained Si ◽  
P Type

scholarly journals High hole mobility in physical vapour deposition-grown tellurium-based transistors

2021 ◽  
Vol 8 (8) ◽  
pp. 210554
Author(s):  
Lin Tao ◽  
Lixiang Han ◽  
Qian Yue ◽  
Bin Yao ◽  
Yujue Yang ◽  
...  
Keyword(s):  
High Performance ◽  
Carrier Mobility ◽  
Vapour Deposition ◽  
Field Effect Transistors ◽  
Transition Metal Dichalcogenides ◽  
High Mobility ◽  
Hole Mobility ◽  
Physical Vapour Deposition ◽  
Metal Dichalcogenides ◽  
P Type

Carrier mobility is one of most important figures of merit for materials that can determine to a large extent the corresponding device performances. So far, extensive efforts have been devoted to the mobility improvement of two-dimensional (2D) materials regarded as promising candidates to complement the conventional semiconductors. Graphene has amazing mobility but suffers from zero bandgap. Subsequently, 2D transition-metal dichalcogenides benefit from their sizable bandgap while the mobility is limited. Recently, the 2D elemental materials such as the representative black phosphorus can combine the high mobility with moderate bandgap; however the air-stability is a challenge. Here, we report air-stable tellurium flakes and wires using the facile and scalable physical vapour deposition (PVD) method. The prototype field-effect transistors were fabricated to exhibit high hole mobility up to 1485 cm 2 V −1 s −1 at room temperature and 3500 cm 2 V −1 s −1 at low temperature (2 K). This work can attract numerous attentions on this new emerging 2D tellurium and open up a new way for exploring high-performance optoelectronics based on the PVD-grown p-type tellurium.

Meso-Epitaxy: Epitaxial Growth Of Silicon Over Buried Single Crystal Cosi2 Layers.

1990 ◽  
Vol 198 ◽  
Author(s):  
J. W. Osenbach ◽  
A. E. White ◽  
K. T. Short ◽  
H. C. Praefcke ◽  
V. C. Kannon
Keyword(s):  
Single Crystal ◽  
Defect Density ◽  
Silicon Layer ◽  
High Dose ◽  
Epitaxial Silicon ◽  
Furnace Annealing ◽  
Good Crystallinity ◽  
Epitaxial Silicon Layer ◽  
P Type ◽  
High Dose Implantation

ABSTRACTBuried single-crystal layers of CoSi2 were formed in 150Ω-cm, p-type (100) silicon by high dose implantation of Co followed by furnace annealing. Subsequently, epitaxial silicon layers were grown over these buried CoSi2 layers using SiCl2H2 /HCI/H2. The RBS channel yield of the buried CoSi2 and the epitaxial Si layer is less than 4% indicating good crystallinity of the layer. The defect density in the epitaxial silicon layer as revealed by a dilute Schimmel etch, was in excess of 108 dislocations/cm2 which appear to originate from <111> CoSi2 facets. However, both the substrate/CoSi2 and the CoSi2/epi interface are single crystal as revealed by lattice fringes in TEM. To our knowledge, this is the first report of such a structure.

Vertical p-type high-mobility heterojunction metal–oxide–semiconductor field-effect transistors

2001 ◽  
Vol 78 (21) ◽  
pp. 3334-3336 ◽  
Author(s):  
Xiangdong Chen ◽  
Qiqing Ouyang ◽  
Sankaran Kartik Jayanarayanan ◽  
Freek E. Prins ◽  
Sanjay Banerjee
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
High Mobility ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
P Type

Channel Engineering of SiGe-Based Heterostructures for High Mobility MOSFETs

2001 ◽  
Vol 686 ◽  
Author(s):  
Christopher W. Leitz ◽  
Matthew T. Currie ◽  
Minjoo L. Lee ◽  
Zhi-Yuan Cheng ◽  
Dimitri. A. Antoniadis ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
High Mobility ◽  
Hole Mobility ◽  
Oxide Semiconductor ◽  
Strained Si ◽  
Alloy Scattering ◽  
Dual Channel ◽  
Significant Performance ◽  
Performance Gains ◽  
Long Channel

AbstractStrained Si- and SiGe-based heterostructure metal-oxide-semiconductor field-effect transistors (MOSFETs) grown on relaxed SiGe virtual substrates exhibit dramatic electron and hole mobility enhancements over bulk Si, making them promising candidates for next generation complementary MOSFET (CMOS) devices. The most heavily investigated heterostructures consist of single strained Si layers grown upon relaxed SiGe substrates. While this configuration offers significant performance gains for both n- and p-MOSFETs, the enhanced hole mobility remains much lower than the enhanced electron mobility. By contrast, a combination of buried compressively strained Si1−yGey layers and tensile strained Si surface layers grown on relaxed Si1−xGex (x < y), hereafter referred to as dual channel heterostructures, offers nearly symmetric electron and hole mobilities without compromising n-MOSFET device performance. To investigate these heterostructures, we study the effects of alloy scattering on channel mobility in long channel MOSFETs. By using the combination of a buried Si0.2Ge0.8 channel and a strained Si surface channel grown on a relaxed Si0.5Ge0.5 virtual substrate, we have achieved nearly symmetric electron and hole mobility in the same heterostructure. By employing different virtual substrate compositions, we can decouple the effects of strain and alloy scattering in both tensile strained surface channels and compressively strained buried channels. We show that significant hole mobility enhancements can be achieved in dual channel heterostructures, even for buried channel compositions where alloy scattering is expected to be most severe. Furthermore, we show that alloy scattering in tensile strained SiGe surface channels impacts electrons much more severely than holes. Taken together, these results demonstrate that dual channel heterostructures can offer symmetric carrier mobilities and provide excellent performance gains for CMOS applications.

Anomalously persistent p-type behavior of WSe2 field-effect transistors by oxidized edge-induced Fermi-level pinning

2022 ◽  
Author(s):  
Tien Dat Ngo ◽  
Min Sup Choi ◽  
Myeongjin Lee ◽  
Fida Ali ◽  
Won Jong Yoo
Keyword(s):  
Fermi Level ◽  
Field Effect ◽  
Field Effect Transistors ◽  
High Mobility ◽  
Two Dimensional ◽  
Edge Contact ◽  
Fermi Level Pinning ◽  
P Type

A technique to form the edge contact in two-dimensional (2D) based field-effect transistors (FETs) has been intensively studied for the purpose of achieving high mobility and also recently overcoming the...

Enhancement of Breakdown Voltage in SOI MOSFET Using Buried p-Type Silicon

2021 ◽  
Author(s):  
Deivakani M ◽  
Sumithra M.G ◽  
Anitha P ◽  
Jenopaul P ◽  
Priyesh P. Gandhi ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Impact Ionization ◽  
Semiconductor Industry ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Physical Models ◽  
Oxide Semiconductor ◽  
Soi Mosfet ◽  
P Type ◽  
Conventional Device

Abstract Semiconductor industry is still looking for the enhancement of breakdown voltage in Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Thus, in this paper, heavy n-type doping below the channel is proposed for SOI MOSFET. Simulation of SOI MOSFET is carried out using 2D TCAD physical simulator. In the conventional device, with no p-type doping is used at the bottom silicon layer. While, in proposed device, p-type doping of 1×1018 cm-3 is used. Physical models are used in the simulation to achieve realistic performance. The models are mobility model, impact ionization model and ohmic contact model. Using TCAD simulation, electron/hole current density, impact generation, recombination and breakdown phenomena are analyzed. It is found that the proposed with p-type doping of 1×1018 cm-3 for SOI MOSFET yields high breakdown voltage. In contrast to conventional device, 20% improvement in breakdown voltage is achieved for proposed device.

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