Meso-Epitaxy: Epitaxial Growth Of Silicon Over Buried Single Crystal Cosi2 Layers.

1990 ◽  
Vol 198 ◽  
Author(s):  
J. W. Osenbach ◽  
A. E. White ◽  
K. T. Short ◽  
H. C. Praefcke ◽  
V. C. Kannon
Keyword(s):  
Single Crystal ◽  
Defect Density ◽  
Silicon Layer ◽  
High Dose ◽  
Epitaxial Silicon ◽  
Furnace Annealing ◽  
Good Crystallinity ◽  
Epitaxial Silicon Layer ◽  
P Type ◽  
High Dose Implantation

ABSTRACTBuried single-crystal layers of CoSi2 were formed in 150Ω-cm, p-type (100) silicon by high dose implantation of Co followed by furnace annealing. Subsequently, epitaxial silicon layers were grown over these buried CoSi2 layers using SiCl2H2 /HCI/H2. The RBS channel yield of the buried CoSi2 and the epitaxial Si layer is less than 4% indicating good crystallinity of the layer. The defect density in the epitaxial silicon layer as revealed by a dilute Schimmel etch, was in excess of 108 dislocations/cm2 which appear to originate from <111> CoSi2 facets. However, both the substrate/CoSi2 and the CoSi2/epi interface are single crystal as revealed by lattice fringes in TEM. To our knowledge, this is the first report of such a structure.

scholarly journals Влияние твердофазной рекристаллизации с двойной имплантацией на плотность структурных дефектов в ультратонких слоях кремния на сапфире

2019 ◽  
Vol 61 (12) ◽  
pp. 2349
Author(s):  
С.Д. Федотов ◽  
В.Н. Стаценко ◽  
Н.Н. Егоров ◽  
С.А. Голубков
Keyword(s):  
Defect Density ◽  
Solid Phase ◽  
Silicon Layer ◽  
Modern Method ◽  
Structural Quality ◽  
Technological Problem ◽  
Recrystallization Process ◽  
Epitaxial Silicon ◽  
Near Surface ◽  
Epitaxial Silicon Layer

The main technological problem in the manufacture of electronics on silicon-on-sapphire (SOS) wafers is the high density of defects in the epitaxial silicon layer. The modern method of obtaining ultrathin SOS wafers using solid-phase epitaxial recrystallization (SPER) and pyrogenic thinning that significantly reduce the defect density in these layers. Nevertheless, the influence of the defect density in submicron SOS layers on the structural quality of ultrathin SOS layers remains unclear. In this work, ultrathin (100 nm) SOS wafers were obtained by SPER of submicron (300 nm) SOS wafers with different structural quality. The crystallinity of 300 nm layers before the recrystallization process and ultrathin layers was determined by XRD and TEM. It was found that the smallest values of the FWHM 0.19-0.20° were observed for the ultrathin SOS layers obtained on the basis of 300 nm SOS wafers with the best structural quality. It was shown that the structural perfect near-surface Si layer, which serves as a seed layer in SPER process, and the double implantation regime allow to reduce the linear defect density in the ultrathin SOS layers by ~ 1×104 cm-1.

Strained Ge Channel p-type MOSFETs Fabricated on Si1−xGex/Si Virtual Substrates

2001 ◽  
Vol 686 ◽  
Author(s):  
Minjoo L. Lee ◽  
Christopher W. Leitz ◽  
Zhiyuan Cheng ◽  
Arthur J. Pitera ◽  
Gianni Taraschi ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
High Mobility ◽  
Silicon Layer ◽  
Hole Mobility ◽  
Oxide Semiconductor ◽  
Epitaxial Silicon ◽  
Wide Range ◽  
Epitaxial Silicon Layer ◽  
P Type ◽  
Mos Device

AbstractWe have fabricated strained Ge channel p-type metal oxide semiconductor field-effect transistors (p-MOSFETs) on Si1−xGex (x=0.7 to 0.9) virtual substrates. Capping the channel with a relaxed, epitaxial silicon layer eliminates the poor interface between silicon dioxide (SiO2) and pure Ge. The effects of the Si cap thickness, the strain in the Ge channel, and the thickness of the Ge channel on hole mobility enhancement were investigated. Optimized strained Ge p-MOSFETs show hole mobility enhancements of nearly 8 times that of co-processed bulk Si devices across a wide range of vertical field. These devices demonstrate that the high mobility holes in strained Ge can be utilized in a MOS device despite the need to cap the channel with a highly dislocated Si layer.

Analysis of Silicon-On-Insulator Structures Formed By Oxygen Ion Implantation

1985 ◽  
Vol 43 ◽  
pp. 300-301
Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Dose ◽  
Crystal Silicon ◽  
Oxygen Ion ◽  
Oxygen Ion Implantation

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

A new soft-error immune DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)

1987 ◽  
Author(s):  
T. Kubota ◽  
T. Ishijima ◽  
M. Sakao ◽  
K. Terada ◽  
T. Hamaguchi ◽  
...  
Keyword(s):  
Silicon Layer ◽  
Soft Error ◽  
Epitaxial Silicon ◽  
Epitaxial Silicon Layer

Supersaturated P-Type Polycrystaline Films Produced by Rapid Thermal Annealing of High Dose Boron Ion Implants for Interconnects and Shallow Junction Diffusion Sources

1990 ◽  
Vol 182 ◽  
Author(s):  
B. Raicu ◽  
M.I. Current ◽  
W.A. Keenan ◽  
D. Mordo ◽  
R. Brennan ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Thermal Annealing ◽  
Cross Section ◽  
Rapid Thermal Annealing ◽  
Single Crystal Silicon ◽  
High Dose ◽  
Crystal Silicon ◽  
Polysilicon Films ◽  
P Type

AbstractHighly conductive p+-polysilicon films were fabricated over Si(100) and SiO2 surfaces using high-dose ion implantation and rapid thermal annealing. Resistivities close to that of single crystal silicon were achieved. These films were characterized by a variety of electrical and optical techniques as well as SIMS and cross-section TEM.

scholarly journals Towards p-type doping of ZnO by ion implantation

2004 ◽  
Vol 829 ◽  
Author(s):  
V. A. Coleman ◽  
H. H. Tan ◽  
C. Jagadish ◽  
S. O. Kucheyev ◽  
M. R. Phillips ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Damage Accumulation ◽  
High Dose ◽  
Furnace Annealing ◽  
Light Emitting ◽  
Selective Area ◽  
Transmission Electron ◽  
Microelectronics Industry ◽  
P Type ◽  
Temperature Furnace

ABSTRACTZinc oxide is a very attractive material for a range of optoelectronic devices including blue light-emitting diodes and laser diodes. Though n-type doping has been successfully achieved, p-type doing of ZnO is still a challenge that must be overcome before p-n junction devices can be realized. Ion implantation is widely used in the microelectronics industry for selective area doping and device isolation. Understanding damage accumulation and recrystallization processes is important for achieving selective area doping. In this study, As (potential p-type dopant) ion implantation and annealing studies were carried out. ZnO samples were implanted with high dose (1.4 × 1017 ions/cm2) 300 keV As ions at room temperature. Furnace annealing of samples in the range of 900°C to 1200°C was employed to achieve recrystallization of amorphous layers and electrical activation of the dopant. Rutherford backscattering/channeling spectrometry, transmission electron microscopy and cathodolumiescence spectroscopy were used to monitor damage accumulation and annihilation behavior in ZnO. Results of this study have significant implications for p-type doing of ZnO by ion implantation.

A New CMOS Structure Using a Transistor on a Lateral Epitaxial Silicon Layer

1988 ◽  
Author(s):  
T. Ishijima ◽  
K. Terada ◽  
T. Kubota ◽  
M. Sakao ◽  
T. Hamaguchi ◽  
...  
Keyword(s):  
Silicon Layer ◽  
Epitaxial Silicon ◽  
Epitaxial Silicon Layer

A Technique for Source/Drain Elevation using Implantation Mediated Selective Etching

2003 ◽  
Vol 765 ◽  
Author(s):  
M. Q. Huda ◽  
K. Sakamoto
Keyword(s):  
Structural Damage ◽  
Low Dose ◽  
Silicon Layer ◽  
Chemical Vapor ◽  
Selective Etching ◽  
Epitaxial Silicon ◽  
Structural Recovery ◽  
Epitaxial Silicon Layer ◽  
Order Of Magnitude ◽  
Polysilicon Layer

AbstractA process involving implantation mediated selective etching has been developed for Source/Drain elevation of CMOS devices. 100 nm thick epitaxial silicon/polysilicon layer was formed on patterned Si/SiO2 structure by chemical vapor deposition (CVD) at 700°C. Structural damage was selectively introduced in polysilicon layer by a low dose Argon implantation at 140 keV. Crystal damage in epitaxial silicon layer was kept minimum by aligning the implantation in vertical <100> channeling direction. A short duration post-anneal at 420°C was usedfor structural recovery of the silicon layer. Polysilicon layer was then removed by wet etching with more than an order of magnitude selectivity over epitaxial silicon. The resulting structure of elevated silicon is free from faceting effects. The process is independent of sidewall/isolation materials, and not bound by thickness limits.

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