Interaction Between Deposited Film Extrinsic Gettering and Intrinsic Gettering in CZ Silicon During Simulated CMOS Process Cycles

1985 ◽  
Vol 59 ◽  
Author(s):  
S. Hahn ◽  
C.-C. D. Wong ◽  
F. A. Ponce ◽  
Z. U. Rek

ABSTRACTThe gettering effectiveness of various thin film structures on n-type CZ silicon wafers has been investigated using electron microscopy, synchrotron radiation topography and optical techniques. Polysilicon, silicon nitride, and poly/nitride films were deposited on etched wafer backsurfaces. The various materials characteristics were correlated with gate oxide breakdown voltage, minority carrier lifetime and yield of MOS capacitors. These studies show that the poly/nitride configuration is superior as a gettering technique.

2013 ◽  
Vol 3 (4) ◽  
pp. 1319-1324 ◽  
Author(s):  
Darius Kuciauskas ◽  
Ana Kanevce ◽  
James M. Burst ◽  
Joel N. Duenow ◽  
Ramesh Dhere ◽  
...  

1986 ◽  
Vol 71 ◽  
Author(s):  
J. Lee ◽  
C. Y. Tung ◽  
S. Hahn ◽  
P. Chiao

AbstractVarious pre-gate oxide cleaning and gettering techniques on the integrity of thin gate oxide were investigated. A 100 Å thick oxide capacitor was used to study its time-dependent breakdown characteristics and minority carrier lifetime. It has been shown that the oxide integrity as measured by time-dependent breakdown and the minority carrier lifetime are very sensitive to the cleaning technique. On the other hand, given adequate cleaning process, different intrinsic gettering schemes may only influence the oxygen precipitation, as well as the minority carrier lifetime, but not the oxide integrity.


MRS Bulletin ◽  
2007 ◽  
Vol 32 (3) ◽  
pp. 225-229 ◽  
Author(s):  
Joseph D. Beach ◽  
Brian E. McCandless

AbstractThe record laboratory cell (∼1 cm2 area) efficiency for thin-film cadmium telluride (CdTe) is 16.5%, and that for a copper indium diselenide (CuInSe2) thin-film alloy is 19.5%. Commercially produced CdTe and CuInSe2 modules (0.5–1 m2 area) have efficiencies in the 7–11% range. Research is needed both to increase laboratory cell efficiencies and to bring those small - area efficiencies to large-area production. Increases in laboratory CdTe cell efficiency will require increasing open-circuit voltage, which will allow cells to harvest more energy from each absorbed photon. This will require extending the minority carrier lifetime from its present τ ≤ 2 ns to τ ≥ 10 ns and increasing hole concentration in the CdTe beyond 1015 cm2, which appears to be limited by compensating defects. Increasing laboratory CuInSe2-based cell efficiency significantly beyond 19.5% will also require increasing the open-circuit voltage, either by increasing the bandgap, the doping level, or the minority carrier lifetime. The photovoltaic cells in commercial modules occupy tens of square centimeters, and both models and experiments have shown that low-performing regions in small fractions of a cell can significantly reduce the overall cell per formance. Increases in commercial module efficiency will require control of materials properties across large deposition areas in a high-throughput environment to minimize such non-uniformities. This article discusses approaches used and research needed to increase the ultimate efficiencies of CdTe- and CuInSe2-based devices and translate these gains to commercial photovoltaic modules.


1987 ◽  
Vol 105 ◽  
Author(s):  
S. Hahn ◽  
C. Y. Tung ◽  
J. Lee ◽  
T. Tuomi ◽  
J. Partanen

AbstractEffects of post-well drive intrinsic gettering (PWIG) upon the integrity of thin gate oxide in Cz Si wafers with carbon levels, Cs, ranged from 0.2 - ∼ 4 ppma were investigated. A 10 nm thick gate oxide capacitor was used to study its time-dependent breakdown characteristics and minority carrier lifetime. Our data have shown that PWIG cycles and/or carbon impurity affect both bulk oxygen precipitation and minority carrier lifetime, but not the oxide integrity.


2001 ◽  
Vol 686 ◽  
Author(s):  
Zengtao Liu ◽  
Chungho Lee ◽  
Gen Pei ◽  
Venkat Narayanan ◽  
Edwin C. Kan

AbstractA technique to form metal nanocrystals on silicon or thin SiO2 film by Rapid Thermal Annealing (RTA) of thin metal film is developed and integrated into standard CMOS processing to make EEPROM devices and improve metal-semiconductor contact resistance. I-V and C-V measurements are carried out on MOSFETs and MOS capacitors containing Au, Ag, Pt, and Si nanocrystals as floating gate for universal mobility and minority carrier lifetime extraction. Mobility around 300 cm2/V-sec and minority carrier lifetime within 0.02 ∼ 0.1 μsec are observed for all cases including the control samples that do not go through the metal nanocrystal formation process, which suggests that the substrate is virtually free from metal contamination. Using this technique, thicker metal film can potentially be achieved as well by stitching thin metal layers on top of the nanocrystals.


2001 ◽  
Vol 707 ◽  
Author(s):  
Zengtao Liu ◽  
Chungho Lee ◽  
Gen Pei ◽  
Venkat Narayanan ◽  
Edwin C. Kan

AbstractA technique to form metal nanocrystals on silicon or thin SiO2 film by Rapid Thermal Annealing (RTA) of thin metal film is developed and integrated into standard CMOS processing to make EEPROM devices and improve metal-semiconductor contact resistance. I-V and C-V measurements are carried out on MOSFETs and MOS capacitors containing Au, Ag, Pt, and Si nanocrystals as floating gate for universal mobility and minority carrier lifetime extraction. Mobility around 300 cm2/V-sec and minority carrier lifetime within 0.02 ∼ 0.1 μsec are observed for all cases including the control samples that do not go through the metal nanocrystal formation process, which suggests that the substrate is virtually free from metal contamination. Using this technique, thicker metal film can potentially be achieved as well by stitching thin metal layers on top of the nanocrystals.


2012 ◽  
Vol 22 (2) ◽  
pp. 180-188 ◽  
Author(s):  
Dominic Walter ◽  
Philipp Rosenits ◽  
Bastian Berger ◽  
Stefan Reber ◽  
Wilhelm Warta

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