In-situ steam generation for shallow trench isolation in sub-100 nm devices

2004 ◽  
Author(s):  
H.J.L. Forstner ◽  
F. Nouri ◽  
C. Olsen
Keyword(s):  
Steam Generation ◽  
Shallow Trench Isolation ◽  
Trench Isolation

Gate-Prior-To-Isolation Cmos-Technology with Through-The-Gate-Implanted Ultra-Thin Gate Oxides

1999 ◽  
Vol 567 ◽  
Author(s):  
Udo Schwalke ◽  
Christian Gruensfelder ◽  
Alexander Gschwandtner ◽  
Gudrun Innertsberger ◽  
Martin Kerber
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Wafer Surface ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Process Architecture ◽  
Process Complexity ◽  
Mos Gate ◽  
Cluster Tool

ABSTRACTWe have realized direct-tunneling gate oxide (1.6nm) NMOS and PMOS transistors by means of through-the-gate-implantation in a comer parasitics-free shallow-trench-isolation CMOS technology. In order to take full advantage of in-situ cluster-tool processing and to preserve initial wafer-surface quality, the essential part of the MOS gate is fabricated prior to device isolation and through-the-gate-implantation is utilized for well- and channel doping. In addition, a fully-reinforced-gate-oxide-perimeter is provided and trench comer parasitics are eliminated by the advanced process architecture EXTIGATE without increasing process complexity.

In-situ Metrology for End Point Detection during Chemical Mechanical Polishing of Shallow Trench Isolation Structure

2005 ◽  
Vol 867 ◽  
Author(s):  
Parshuram B. Zantye ◽  
S. Mudhivarthi ◽  
Ashok Kumar ◽  
David Evans
Keyword(s):  
Chemical Mechanical Polishing ◽  
Mechanical Polishing ◽  
Shallow Trench Isolation ◽  
End Point ◽  
Trench Isolation ◽  
End Point Detection ◽  
In Situ Metrology ◽  
Point Detection

AbstractEfficient end point detection (EPD) helps prevent numerous Chemical Mechanical Polishing (CMP) process defects such as dishing, erosion, excessive over-polish etc. During the CMP of Shallow Trench Isolation (STI) structures, the process should be effectively stopped at the buried Si3N4 layer to prevent any/all of the aforementioned process defects. In this research, novel in-situ metrology technique that used the real time tracking of Coefficient of Friction (COF) data during polishing was employed for EPD during STI-CMP. The experiments were performed on the CETR CP-4 CMP Tester using 1“X 1” sample coupons having a 2 ‘mu;m pitch STI pattern. The COF signal during polishing is a characteristic signature of the given process parameters and conditions. The in-situ EPD was based on the principle that the COF values are strongly dependent upon the surface of the materials that are being polished. Extended polishing to polish the underlying layer after the process end point was reached, can give an estimate of the polishing slurry selectivity with respect to the buried layer. The ex-situ surface characterization of coupons was performed at different points of the process using Atomic Force Microscopy (AFM). The repeatability and reliability of this technique was evaluated after carrying out multiple tests at similar process conditions. The demonstrated methodology can also be implemented for characterization of polishing pads and slurries besides STI-CMP process optimization.

Micro-Raman Spectroscopy Evaluation of the Local Mechanical Stress in Shallow Trench Isolation CMOS Structures: Correlation with Defect Generation and Diode Leakage

1998 ◽  
Author(s):  
I. De Wolf ◽  
G. Groeseneken ◽  
H.E. Maes ◽  
M. Bolt ◽  
K. Barla ◽  
...  
Keyword(s):  
Raman Spectroscopy ◽  
Mechanical Stress ◽  
Defect Formation ◽  
Active Area ◽  
Wet Oxidation ◽  
Leakage Currents ◽  
Shallow Trench Isolation ◽  
Micro Raman Spectroscopy ◽  
Silicon Devices ◽  
Trench Isolation

Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.

Advances in Chemical-Mechanical Planarization

MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 743-751 ◽  
Author(s):  
Rajiv K. Singh ◽  
Rajeev Bajaj
Keyword(s):  
Surface Topography ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Chemical Mechanical Planarization ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Fundamental Understanding ◽  
Copper Polishing ◽  
Future Growth

AbstractThe primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.

Analysis of Self-Heating Effects on vertical FET according to Shallow Trench Isolation

2017 ◽  
Vol 137 ◽  
pp. 123-127
Author(s):  
Ilho Myeong ◽  
Dokyun Son ◽  
Hyunsuk Kim ◽  
Myounggon Kang ◽  
Hyungcheol Shin
Keyword(s):  
Shallow Trench Isolation ◽  
Self Heating ◽  
Heating Effects ◽  
Trench Isolation
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