Deposition and Treatment of TiO2 as an Alternative for Ultrathin Gate Dielectrics

1999 ◽  
Vol 567 ◽  
Author(s):  
Yanjun Ma ◽  
Yoshi Ono ◽  
Sheng Teng Hsu
Keyword(s):  
Leakage Current ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Desirable Property ◽  
Post Deposition Annealing ◽  
Plasma Exposure ◽  
Thermal Budget ◽  
Gate Electrodes ◽  
Post Deposition

ABSTRACTWe investigated the use of TiO2 as an alternate gate dielectric for future CMOS applications. To reduce the leakage current, different post deposition treatments were investigated. It was found that for very thin TiO2 films, ozone plasma exposure is an effective way in lowering thermal budget of the post deposition annealing. Doping TiO2with Si and/or Al can also be effective in substantially reducing the leakage current. In addition, the doped TiO2 has the desirable property of remaining amorphous even after anneal at 850°C. We also report the fabrication of submicron MOSFETs with TiO2 gate dielectrics equivalent to 2 nm of SiO2 and TiN/Cu gate electrodes.

Effect of the post-deposition annealing on electrical characteristics of MIS structures with HfO2/SiO2 gate dielectric stacks

2012 ◽  
Vol 177 (15) ◽  
pp. 1281-1285 ◽  
Author(s):  
Andrzej Taube ◽  
Robert Mroczyński ◽  
Katarzyna Korwin-Mikke ◽  
Sylwia Gierałtowska ◽  
Jan Szmidt ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Electrical Characteristics ◽  
Post Deposition Annealing ◽  
Post Deposition ◽  
Mis Structures

Electrical Characteristics of LaAlO[sub 3] Gate Dielectrics Prepared by High-Pressure Hydrogen Post-Deposition Annealing

2006 ◽  
Vol 9 (11) ◽  
pp. F77 ◽  
Author(s):  
Musarrat Hasan ◽  
Min Seok Jo ◽  
Md. Shahriar Rahman ◽  
Hyejong Choi ◽  
Sungho Heo ◽  
...  
Keyword(s):  
High Pressure ◽  
Gate Dielectrics ◽  
Electrical Characteristics ◽  
Post Deposition Annealing ◽  
Post Deposition ◽  
Pressure Hydrogen

Electrical Properties of Stacked RTO/RTCVD Oxides as Gate Dielectrics

1994 ◽  
Vol 342 ◽  
Author(s):  
V. Misra ◽  
X-L. Xu ◽  
J.J. Wortman
Keyword(s):  
Gate Dielectric ◽  
Defect Density ◽  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Single Layer ◽  
Superior Performance ◽  
Potential Candidate ◽  
Thermal Budget ◽  
Thermal Oxide

ABSTRACTTo meet the stringent demands of high quality gate performance in advanced devices, a more robust gate dielectric is needed. A stacked structure consisting of thermal oxide and deposited oxide is a potential candidate since it offers certain advantages over single layer oxides such as 1) reduced defect density, 2) reduced stress at the SiO2/Si interface due to stress compensation between the thermal and the deposited oxide, 3) less silicon consumption and 4) reduced thermal budget. In this study, stacked oxides consisting of RTO and RTCVD oxides are characterized. In contrast to other studies which use conventional LPCVD methods to form the top oxide, these stacked oxides have the advantages of rapid thermal and in-situ processing, which produces excellent bulk and interfacial properties. Electrical characterization has shown that these stacked oxides have superior performance compared to single layer furnace or deposited oxides.

Impact of Gate Process Technology on EOT of HfO2 Gate Dielectric

2003 ◽  
Vol 765 ◽  
Author(s):  
Daewon Ha ◽  
Qiang Lu ◽  
Hideki Takeuchi ◽  
Tsu-Jae King ◽  
Katsunori Onishi ◽  
...  
Keyword(s):  
Leakage Current ◽  
Deposition Rate ◽  
Silicon Germanium ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Cmos Process ◽  
Gate Leakage ◽  
Process Technology ◽  
Cmos Scaling

AbstractTo facilitate CMOS scaling beyond the 65 nm technology node, high-permittivity gate dielectrics such as HfO2 will be needed in order to achieve sub-1.3nm equivalent oxide thickness (EOT) with suitably low gate leakage, particularly for low-power applications. Polycrystalline silicon-germanium (poly-SiGe) is a promising gate material because it is compatible with a conventional CMOS process flow, and because it can yield significantly lower electrical gate-oxide thickness as compared with poly-Si. In this paper, the effects of the gate material (Si vs. SiGe) and gate deposition rate on EOT and gate leakage current density are investigated. Poly-Si0.75Ge0.25 gate material yields the lowest EOT and is stable up to 950°C for 30 seconds, providing 2 orders of magnitude lower leakage current compared to poly-Si gate material. A faster gate deposition rate (achieved by using S2H6 instead of SiH4 as the gaseous Si source) is also effective for minimizing the increases in EOT and leakage current with high-temperature annealing.

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