Investigation of the Role of Chemical-Mechanical Polishing in Improving the Performance of Polysilicon TFTs

1999 ◽  
Vol 558 ◽  
Author(s):  
B. Lee ◽  
L.J. Quinn ◽  
P.T. Baine ◽  
S.J.N. Mitchell ◽  
B.M. Armstrong ◽  
...  
Keyword(s):  
Thin Film ◽  
Surface Roughness ◽  
Chemical Mechanical Polishing ◽  
Carrier Transport ◽  
Gate Dielectric ◽  
Thin Film Transistor ◽  
Mechanical Polishing ◽  
Initial Surface ◽  
Silicon Thin Film ◽  
Glass Substrates

ABSTRACTPolycrystalline silicon thin-film transistors (TFTs) have been fabricated on glass substrates using a low temperature top-gate self-aligned process. The interface between the polysilicon active layer and the silicon dioxide oxide gate dielectric is of vital importance in order to achieve good thin-film transistor electrical characteristics. Carrier transport takes place within 10nm of this interface, and any roughness in this region, corresponding to the initial surface roughness of the polysilicon layer, causes scattering of the carriers and a higher density of interface traps. Chemical-mechanical polishing has been used to reduce the initial surface roughness of the polysilicon. Electrical parameters of polished TFTs, such as mobility and threshold voltage, show a marked improvement compared to unpolished devices.

Thin-Film Transistors on PET at 100°C

2002 ◽  
Vol 715 ◽  
Author(s):  
J.P. Conde ◽  
P. Alpuim ◽  
V. Chu
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Contact Layer ◽  
Processing Temperature ◽  
Silicon Thin Film ◽  
Glass Substrates ◽  
Hydrogen Dilution ◽  
Polyethylene Terephthalate Substrate

AbstractBottom-gate amorphous silicon thin-film transistors were fabricated on a polyethylene terephthalate substrate. The maximum processing temperature was 100°C. The transistor characteristics are comparable, although still inferior, to those of standard amorphous silicon transistors fabricated on glass substrates. To obtain these characteristics, an extended anneal the processing temperature was required. The devices were fabricated using separately optimized low-temperature active layer, contact layer and gate dielectric layer. To achieve good electronic properties for these layers, hydrogen dilution was required.

Electrical Characteristics of Low-Temperature Poly-Silicon Thin-Film Transistor Using a Stacked Pr2O3/SiOxNy Gate Dielectric

2019 ◽  
Vol 13 (1) ◽  
pp. 151-155
Author(s):  
Tung-Ming Pan ◽  
Tin-Wei Wu ◽  
Ching-Lin Chan ◽  
Kai-Ming Chen ◽  
Chih-Hong Lee
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Gate Dielectric ◽  
Thin Film Transistor ◽  
Electrical Characteristics ◽  
Silicon Thin Film ◽  
Poly Silicon

Optimizing polysilicon thin-film transistor performance with chemical-mechanical polishing and hydrogenation

1996 ◽  
Vol 17 (11) ◽  
pp. 518-520 ◽  
Author(s):  
A.B.Y. Chan ◽  
C.T. Nguyen ◽  
P.K. Ko ◽  
Man Wong ◽  
A. Kumar ◽  
...  
Keyword(s):  
Thin Film ◽  
Chemical Mechanical Polishing ◽  
Thin Film Transistor ◽  
Mechanical Polishing

Fabrication of a-Si:H Tfts at 120°C on Flexible Polyimide Substrates

1999 ◽  
Vol 558 ◽  
Author(s):  
Andrei Sazonov ◽  
Arokia Nathan ◽  
R.V.R. Murthy ◽  
S.G. Chamberlain
Keyword(s):  
Thin Film ◽  
Gate Dielectric ◽  
Low Cost ◽  
Thin Film Transistor ◽  
Performance Comparison ◽  
Hydrogen Gas ◽  
Large Area ◽  
Plastic Substrates ◽  
Glass Substrates ◽  
Contact Metallization

ABSTRACTThe fabrication of large-area thin-film transistor (TFT) arrays on thin flexible plastic substrates requires deposition of thin film layers at relatively low temperatures since the upper working temperature of low-cost plastic films should not exceed ∼200°C. In this paper, we report a fabrication process of a-Si:H TFTs at 120°C on flexible polyimide substrates for large-area imaging applications.Kapton HN (DuPont) films 50 and 125 μm thick and 3 inches in diameter, were used as substrates. Both sides of the polyimide substrate were first covered with 0.5 μm thick a-SiNx. The TFT structure includes: 120 nm thick room-temperature sputtered Al gate, 250 nm thick PECVD deposited a-SiNx for the gate dielectric, 50 nm thick a-Si:H deposited by PECVD from silane-hydrogen gas mixture, 50 nm thick n+ a-Si:H source- and drain contacts, and roomtemperature sputtered Al top contact metallization. We used dry etching for all layers except for the gate and top metal, which were patterned using wet etchants. For purpose of TFT performance comparison, Coming 7059 glass substrates were used.The performance of the fabricated TFT and its improvement with use of optimized a-Si:H and a-SiNx quality will be presented along with a discussion of the intrinsic mechanical stress in the thin film layers will also be discussed.

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