Improvement of the surface roughness and sensing properties of cerium dioxide thin film by chemical mechanical polishing

2008 ◽  
Vol 26 (4) ◽  
pp. 794-797 ◽  
Author(s):  
Nam-Hoon Kim ◽  
Pil-Ju Ko ◽  
Woo-Sun Lee
Keyword(s):  
Thin Film ◽  
Surface Roughness ◽  
Chemical Mechanical Polishing ◽  
Cerium Dioxide ◽  
Mechanical Polishing ◽  
Sensing Properties

Investigation of the Role of Chemical-Mechanical Polishing in Improving the Performance of Polysilicon TFTs

1999 ◽  
Vol 558 ◽  
Author(s):  
B. Lee ◽  
L.J. Quinn ◽  
P.T. Baine ◽  
S.J.N. Mitchell ◽  
B.M. Armstrong ◽  
...  
Keyword(s):  
Thin Film ◽  
Surface Roughness ◽  
Chemical Mechanical Polishing ◽  
Carrier Transport ◽  
Gate Dielectric ◽  
Thin Film Transistor ◽  
Mechanical Polishing ◽  
Initial Surface ◽  
Silicon Thin Film ◽  
Glass Substrates

ABSTRACTPolycrystalline silicon thin-film transistors (TFTs) have been fabricated on glass substrates using a low temperature top-gate self-aligned process. The interface between the polysilicon active layer and the silicon dioxide oxide gate dielectric is of vital importance in order to achieve good thin-film transistor electrical characteristics. Carrier transport takes place within 10nm of this interface, and any roughness in this region, corresponding to the initial surface roughness of the polysilicon layer, causes scattering of the carriers and a higher density of interface traps. Chemical-mechanical polishing has been used to reduce the initial surface roughness of the polysilicon. Electrical parameters of polished TFTs, such as mobility and threshold voltage, show a marked improvement compared to unpolished devices.

Development of TSV Reveal Process Using Very Fine Si/Cu Grinding and Metal Contamination Removal

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001928-001955
Author(s):  
Naoya Watanabe ◽  
Masahiro Aoyagi ◽  
Daisuke Katagawa ◽  
Tsubasa Bandoh ◽  
Takahiko Mitsui ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Chemical Mechanical Polishing ◽  
Metal Contamination ◽  
Mechanical Polishing ◽  
Grinding Wheel ◽  
Average Surface Roughness ◽  
Average Surface ◽  
3D Ics ◽  
Cu Contamination ◽  
Contamination Removal

Three-dimensional integrated circuits (3D-ICs) using through silicon via (TSV) have been developed as an emerging technology that can lead to significant progress (1–4). Among various TSV processes, the via-middle process has potential for wide spread use because formation of small-sized TSVs is relatively easy in the via-middle process. However, TSV reveal process must be performed for electrical contact in the via-middle process. This TSV reveal process is important because it can influence the metal contamination and stacking yield of 3D-ICs. Conventionally, TSV reveal is performed by Si grinding and Si dry etching (5). A disadvantage of that method is the resultant TSV depth deviation, which can cause bonding failure during wafer/chip stacking. In (6), TSV leveling was performed by introducing a chemical mechanical polishing (CMP) step after deposition of the backside insulator. However, the revealed TSVs break during CMP step if they exceed a certain height. To overcome these problems, we developed a novel TSV reveal process comprising direct Si/Cu grinding and metal contamination removal (7,8). First, simultaneous grinding of Cu and Si was performed using a novel vitrified grinding wheel. In situ cleaning with a high-pressure micro jet and the inelastic porous structure of the grinding wheel suppressed the adhesion of Cu contaminants to the Si, and TSVs were leveled and exposed. Next, an electroless Ni-B film was deposited on the Cu surface of the TSVs. The Si was etched with an alkaline solution, whereas the Cu was protected by the Ni-B film. An insulator was deposited, and then the insulator on the top surface of the TSV was removed. We achieved the backside reveal of TSVs without TSV depth deviation and suppressed Cu contamination to less than 1e11 atoms/cm2. However, after direct Si/Cu grinding with an 8000 grit grinding wheel, the average surface roughness of Si was 5–10 nm, which is larger than that after chemical mechanical polishing (CMP). In this paper, we developed vitrified grinding wheels with very high grit numbers (#30,000 and #45,000) and present an improved version of our TSV reveal process. The average surface roughness of Si after Si/Cu grinding was approximately 3 nm for the 30,000 grit grinding wheel and 1 nm for the 45,000 grit grinding wheel. This value is equivalent to that after CMP. The improved process produced a uniform reveal of 4-um-diameter TSVs without TSV depth deviation and Cu contamination. The Cu contaminant concentration on Si region between TSVs was small (<3e10 atoms/cm2). This process will reduce the cost of the TSV reveal process and considerably improve the TSV yield.

Blade Diamond Disk for Conditioning CMP Polishing Pad

2010 ◽  
Vol 97-101 ◽  
pp. 3-6 ◽  
Author(s):  
Ming Yi Tsai
Keyword(s):  
Surface Roughness ◽  
Epoxy Resin ◽  
Chemical Mechanical Polishing ◽  
Polycrystalline Diamond ◽  
Mechanical Polishing ◽  
Height Variation ◽  
Surface Textures ◽  
Diamond Disk ◽  
Diamond Conditioner ◽  
The Cost

A diamond conditioner or dresser is needed to regenerate the asperity structure of the pad and recover its designed ability in chemical mechanical polishing (CMP) process. In this paper a new design of diamond conditioner is made by shaping a sintered matrix of polycrystalline diamond (PCD) to form teethed blades. These blades are arranged and embedded in epoxy resin to make a designed penetration angle, called the blade diamond disk. The dressing characteristics of pad surface textures are studied by comparison with conventional diamond conditioner. It is found that the height variation of the diamond tip of blade diamond disk is significantly smaller than the conventional diamond disk. The dressing rate of blade diamond disk is lower than that of the conventional diamond disk, and hence the pad life is prolonged. As a result, reduction of the cost CMP is expected. In addition the pad surface roughness Ra of about 3.79μm is less than Ra of about 4.15μm obtained after dressing using a conventional diamond disk.

Chemical Mechanical Polishing on Extremely Low Expansion Glass Ceramic Wafers

2016 ◽  
Vol 874 ◽  
pp. 389-394 ◽  
Author(s):  
Zhi Feng Shi ◽  
Zhen Yu Zhang ◽  
Si Ling Huang ◽  
Bo Ya Yuan ◽  
Xiao Guang Guo ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Integrated Circuit ◽  
Glass Ceramic ◽  
Chemical Mechanical Polishing ◽  
High Performance ◽  
Ph Value ◽  
Liquid Crystal Display ◽  
Glass Ceramics ◽  
Mechanical Polishing ◽  
High Precision Measurement

Extremely low expansion glass ceramics are widely used in integrated circuit (IC), liquid crystal display (LCD) lithography, high-precision measurement and astronomy, due to their excellent mechanical properties and chemical stability at higher temperatures. Nevertheless, the extremely low expansion glass ceramics are hard-to-machine materials due to their hard-brittle nature, resulting in cracking, chipping and scratching induced in conventional machining. This leads to higher surface roughness, and is not qualified for high-performance devices. In this study, surface roughness of 0.447 and 4.904 nm are achieved for Ra and peak-to valley (PV), respectively with a measurement area of 70×53 μm2 after chemical mechanical polishing (CMP). Firstly, the glass ceramic wafers are lapped using silicon carbide (SiC) abrasives on a cast-iron plate. After lapping, the wafers are polished by CeO2 slurry in a sequence of 3 μm and 500 nm in diameter, and polyurethane and floss pads are used correspondingly. Finally, CMP is employed on the glass ceramic wafers. Floss pad and silica slurry are used in CMP in an alkaline solution with a pH value of 8.5. After CMP, the wafers are cleaned and dried by deionized wafer and compressed air, respectively.

Environment-Friendly Chemical Mechanical Polishing Slurry for SiC Wafer

2016 ◽  
Vol 874 ◽  
pp. 415-419
Author(s):  
Ze Wei Yuan ◽  
Yan He ◽  
Quan Wen ◽  
Hai Yang Du
Keyword(s):  
Surface Roughness ◽  
Reaction Mechanism ◽  
Environmental Pollution ◽  
Chemical Mechanical Polishing ◽  
Mechanical Polishing ◽  
Polishing Process ◽  
Environment Friendly ◽  
High Efficient ◽  
Sic Wafer

In order to avoid the environmental pollution and the harm to body of traditional polishing slurries, an environment-friendly chemical mechanical polishing technology is proposed for SiC wafer in this study. With this method, SiC material is removed by utilizing the strong oxidability of nanotitanium dioxide particles in chemical mechanical slurry in the existence of ultraviolet. While, the oxidbillity will recede in absence of ultraviolet when the polishing process finishes. On the basis of investigating in the reaction mechanism between SiC and nanotitanium dioxide, the slurries are prepared for the environment-friendly chemical mechanical polishing technology. The results show that the ultraviolet-assisted CMP slurry has strong oxidation for SiC material. This method is high-efficient for polishing SiC wafer. The surface roughness is reduced to about Ra 0.1μm from Ra 0.818μm after polishing for one hour.

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