Nonvolatile Amorphous Silicon Thin Film Transistor Memories with the a-Si:H Embedded Gate Dielectric Structure

2019 ◽  
Vol 3 (8) ◽  
pp. 333-339 ◽  
Author(s):  
Yue Kuo ◽  
Helinda Nominanda
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Gate Dielectric ◽  
Thin Film Transistor ◽  
Dielectric Structure ◽  
Silicon Thin Film

Amorphous-silicon thin film transistor with two-step exposure process

2000 ◽  
Author(s):  
Pi-Fu Chen ◽  
Jr-Hong Chen ◽  
Dou-I Chen ◽  
HsixgJu Sung ◽  
June-Wei Hwang ◽  
...  
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistor ◽  
Silicon Thin Film ◽  
Exposure Process

Hot-Wire Deposited Amorphous Silicon Thin-Film Transistors

1996 ◽  
Vol 424 ◽  
Author(s):  
R. E. I. Schropp ◽  
K. F. Feenstra ◽  
C. H. M. Van Der Werf ◽  
J. Holleman ◽  
H. Meiling
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Chemical Vapor ◽  
Current Crowding ◽  
Hot Wire ◽  
Saturation Regime ◽  
Silicon Thin Film ◽  
Order Of Magnitude

AbstractWe present the first thin film transistors (TFTs) incorporating a low hydrogen content (5 - 9 at.-%) amorphous silicon (a-Si:H) layer deposited by the Hot-Wire Chemical Vapor Deposition (HWCVD) technique. This demonstrates the possibility of utilizing this material in devices. The deposition rate by Hot-Wire CVD is an order of magnitude higher than by Plasma Enhanced CVD. The switching ratio for TFTs based on HWCVD a-Si:H is better than 5 orders of magnitude. The field-effect mobility as determined from the saturation regime of the transfer characteristics is still quite poor. The interface with the gate dielectric needs further optimization. Current crowding effects, however, could be completely eliminated by a H2 plasma treatment of the HW-deposited intrinsic layer. In contrast to the PECVD reference device, the HWCVD device appears to be almost unsensitive to bias voltage stressing. This shows that HW-deposited material might be an approach to much more stable devices.

Low frequency noise in amorphous silicon thin film transistors with SiNx gate dielectric

2009 ◽  
Vol 105 (12) ◽  
pp. 124504 ◽  
Author(s):  
S. L. Rumyantsev ◽  
Sung Hun Jin ◽  
M. S. Shur ◽  
Mun-Soo Park
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Low Frequency ◽  
Frequency Noise ◽  
Low Frequency Noise ◽  
Silicon Thin Film

Hydrogenation Effect of Amorphous Silicon Thin Film Transistors by Atmospheric Pressure CVD

1993 ◽  
Vol 297 ◽  
Author(s):  
Byung Chul Ahn ◽  
Jeong Hyun Kim ◽  
Dong Gil Kim ◽  
Byeong Yeon Moon ◽  
Kwang Nam Kim ◽  
...  
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Atmospheric Pressure ◽  
Thin Film Transistors ◽  
Field Effect ◽  
Low Cost ◽  
Thin Film Transistor ◽  
Field Effect Mobility ◽  
Silicon Thin Film ◽  
Hydrogenation Effect

The hydrogenation effect was studied in the fabrication of amorphous silicon thin film transistor using APCVD technique. The inverse staggered type a-Si TFTs were fabricated with the deposited a-Si and SiO2 films by the atmospheric pressure (AP) CVD. The field effect mobility of the fabricated a-Si TFT is 0.79 cm2/Vs and threshold voltage is 5.4V after post hydrogenation. These results can be applied to make low cost a-Si TFT array using an in-line APCVD system.

A Center-Offset Polycrystalline-Silicon Thin-Film Transistor With ${\rm n}^{+}$ Amorphous-Silicon Contacts

2009 ◽  
Vol 30 (1) ◽  
pp. 36-38 ◽  
Author(s):  
J. H. Oh ◽  
D. H. Kang ◽  
W. H. Park ◽  
J. Jang ◽  
Y. J. Chang ◽  
...  
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Polycrystalline Silicon ◽  
Thin Film Transistor ◽  
Silicon Thin Film

Study on Light Induced Leakage Current Related to Amorphous Silicon TFT Design

2007 ◽  
Vol 124-126 ◽  
pp. 259-262
Author(s):  
Jae Hong Jeon ◽  
Kang Woong Lee
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Leakage Current ◽  
Thin Film Transistor ◽  
Silicon Layer ◽  
Gate Electrode ◽  
Silicon Thin Film ◽  
Pattern Design ◽  
Conventional Design ◽  
The One

We investigated the effect of amorphous silicon pattern design regarding to light induced leakage current in amorphous silicon thin film transistor. In addition to conventional design, where amorphous silicon layer is protruding outside the gate electrode, we designed and fabricated amorphous silicon thin film transistors in another two types of bottom gated structure. The one is that the amorphous silicon layer is located completely inside the gate electrode and the other is that the amorphous silicon layer is protruding outside the gate electrode but covered completely by the source and drain electrode. Measurement of the light induced leakage current caused by backlight revealed that the design where the amorphous silicon is located inside the gate electrode was the most effective however the last design was also effective in reducing the leakage current about one order lower than that of the conventional design.

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