Alternative Gate Dielectrics with BST/TIO2/(Barrier Oxide) Stacked Structure

1998 ◽  
Vol 525 ◽  
Author(s):  
Yongjoo Jeon ◽  
Byoung Hun Lee ◽  
Keith Zawadzki ◽  
Wen-Jie Qi ◽  
Jack C. Lee
Keyword(s):  
Leakage Current ◽  
Barrier Layer ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Tunneling Current ◽  
Annealing Conditions ◽  
Higher Temperature ◽  
Direct Tunneling Current ◽  
Mis Capacitors

ABSTRACTBST/TiO2/(Barrier Layer) stacked dielectric structure has been proposed for ultra thin (<20Å) gate dielectric application to overcome the direct tunneling current problem of Si02. To characterize the alternative dielectrics, MIM and MIS capacitors were fabricated. TiO2 is believed to prevent BST and Si from reaction and interdiffusion while TiC2 itself is stable due to the strong binding energy. For better interfacial quality of TiO2/Si interface, proper barrier layer is needed between TiO2 and Si. Optimization of this barrier layer was performed by RTP grown N20 oxide and self-grown interfacial oxide layer with various annealing conditions. To monitor these barrier layers, TEM and electrical analysis were performed. From TEM observation, it was found that interfacial layer was formed in every sample whether it was intentionally grown or not. It was observed that the leakage current of Pt/TiO2/Si dramatically increased after 700'C or higher temperature annealing. This might be related to the transition of crystal structure of TiO2 from anatese to rutile at about 700°C[1]. It was also found that both Pt/BST/TiO2/Si and Pt/TiO2/Si showed lower leakage current compare to the conventional NO oxide at comparable equivalent SiO2 thickness. These results imply that these materials hold some promise as alternatives of pure SiO2 in very thin range.

Improvement in Gate Dielectric Quality of Ultra Thin a: SiN:H MNS Capacitor by Hydrogen Etching of the Substrate

2002 ◽  
Vol 716 ◽  
Author(s):  
Parag C. Waghmare ◽  
Samadhan B. Patil ◽  
Rajiv O. Dusane ◽  
V.Ramgopal Rao
Keyword(s):  
Silicon Nitride ◽  
Gate Dielectric ◽  
Substrate Surface ◽  
Scaling Limit ◽  
Tunneling Current ◽  
Chemical Vapor ◽  
Poor Performance ◽  
State Density ◽  
Direct Tunneling Current

AbstractTo extend the scaling limit of thermal SiO2, in the ultra thin regime when the direct tunneling current becomes significant, members of our group embarked on a program to explore the potential of silicon nitride as an alternative gate dielectric. Silicon nitride can be deposited using several CVD methods and its properties significantly depend on the method of deposition. Although these CVD methods can give good physical properties, the electrical properties of devices made with CVD silicon nitride show very poor performance related to very poor interface, poor stability, presence of large quantity of bulk traps and high gate leakage current. We have employed the rather newly developed Hot Wire Chemical Vapor Deposition (HWCVD) technique to develop the a:SiN:H material. From the results of large number of optimization experiments we propose the atomic hydrogen of the substrate surface prior to deposition to improve the quality of gate dielectric. Our preliminary results of these efforts show a five times improvement in the fixed charges and interface state density.

Enhanced Phonon-Energy Coupling: Dramatic Reduction of Leakage Current of Silicon Oxide

2006 ◽  
Vol 917 ◽  
Author(s):  
Zhi Chen ◽  
Jun Guo ◽  
Chandan B Samantaray
Keyword(s):  
Effective Mass ◽  
Leakage Current ◽  
Thermal Processing ◽  
Silicon Oxide ◽  
Tunneling Current ◽  
Energy Coupling ◽  
Phonon Energy ◽  
Gate Leakage Current ◽  
Ultrathin Oxides ◽  
Direct Tunneling Current

AbstractWe study in detail a newly discovered effect, phonon-energy-coupling enhancement (PECE) effect, produced by rapid thermal processing (RTP). It includes two aspects: (1) Strengthening Si-D bonds and Si-O bonds and (2) Change of energy band structure and effective mass due to thermal shock. It is shown that not only Si-D bonds but also Si-O bonds have been strengthened dramatically, leading to enhancement of robustness of the oxide structure and the oxide/Si interface. For thick oxides (>3 nm), the gate leakage current has been reduced by two orders of magnitude and the breakdown voltage has been improved by ~30% due to phonon-energy coupling. For ultrathin oxides (2.2 nm), the direct tunneling current has been reduced by five-orders of magnitude, equivalent to that of HfO2, probably due to the increased effective mass and barrier height.

scholarly journals Q-Factor Performance of 28 nm-Node High-K Gate Dielectric under DPN Treatment at Different Annealing Temperatures

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2086
Author(s):  
Chii-Wen Chen ◽  
Shea-Jue Wang ◽  
Wen-Ching Hsieh ◽  
Jian-Ming Chen ◽  
Te Jong ◽  
...  
Keyword(s):  
Figure Of Merit ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Nitrogen Concentration ◽  
Point Of View ◽  
Tunneling Effect ◽  
Q Factor ◽  
High K ◽  
Different Temperatures

Q-factor is a reasonable index to investigate the integrity of circuits or devices in terms of their energy or charge storage capabilities. We use this figure of merit to explore the deposition quality of nano-node high-k gate dielectrics by decoupled-plasma nitridation at different temperatures with a fixed nitrogen concentration. This is very important in radio-frequency applications. From the point of view of the Q-factor, the device treated at a higher annealing temperature clearly demonstrates a better Q-factor value. Another interesting observation is the appearance of two troughs in the Q-VGS characteristics, which are strongly related to either the series parasitic capacitance, the tunneling effect, or both.

Interface Quality and Electrical Performance of Low-Temperature Metal Organic Chemical Vapor Deposition Aluminum Oxide Thin Films for Advanced CMOS Gate Dielectric Applications

2002 ◽  
Vol 745 ◽  
Author(s):  
Spyridon Skordas ◽  
Filippos Papadatos ◽  
Steven Consiglio ◽  
Eric Eisenbraun ◽  
Alain Kaloyeros
Keyword(s):  
Dielectric Constant ◽  
Leakage Current ◽  
Gate Dielectric ◽  
Chemical Vapor ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Organic Chemical ◽  
Si Substrates ◽  
Annealing Conditions ◽  
Metal Organic

ABSTRACTIn this work, the electrical performance and interfacial characteristics of MOCVD-grown Al2O3 films are evaluated. Electrical characteristics (dielectric constant, leakage current) of as-deposited and annealed capacitor metal-oxide-semiconductor (MOS) stacks were determined using capacitance-voltage (C-V) and current-voltage (I-V) measurements. It was observed that the electrical properties were dependent upon specific annealing conditions, with an anneal in O2 followed by forming gas being superior with respect to leakage current, resulting in leakage characteristics superior to those of SiO2. All annealing conditions evaluated led to an increase in dielectric constant from 6.5 to 9.0–9.8. Also, Al2O3 growth and interfacial oxide growth characteristics on oxynitride/Si and Si substrates were evaluated and compared using spectroscopic ellipsometry. A parasitic oxide layer was observed to form on silicon during the initial stages of MOCVD Al2O3 growth, while a thin oxynitride layer deposited on Si prevented the growth of interfacial oxide.

Impact of Gate Process Technology on EOT of HfO2 Gate Dielectric

2003 ◽  
Vol 765 ◽  
Author(s):  
Daewon Ha ◽  
Qiang Lu ◽  
Hideki Takeuchi ◽  
Tsu-Jae King ◽  
Katsunori Onishi ◽  
...  
Keyword(s):  
Leakage Current ◽  
Deposition Rate ◽  
Silicon Germanium ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Cmos Process ◽  
Gate Leakage ◽  
Process Technology ◽  
Cmos Scaling

AbstractTo facilitate CMOS scaling beyond the 65 nm technology node, high-permittivity gate dielectrics such as HfO2 will be needed in order to achieve sub-1.3nm equivalent oxide thickness (EOT) with suitably low gate leakage, particularly for low-power applications. Polycrystalline silicon-germanium (poly-SiGe) is a promising gate material because it is compatible with a conventional CMOS process flow, and because it can yield significantly lower electrical gate-oxide thickness as compared with poly-Si. In this paper, the effects of the gate material (Si vs. SiGe) and gate deposition rate on EOT and gate leakage current density are investigated. Poly-Si0.75Ge0.25 gate material yields the lowest EOT and is stable up to 950°C for 30 seconds, providing 2 orders of magnitude lower leakage current compared to poly-Si gate material. A faster gate deposition rate (achieved by using S2H6 instead of SiH4 as the gaseous Si source) is also effective for minimizing the increases in EOT and leakage current with high-temperature annealing.

The Study of Direct Tunneling Current in Strained MOS Device with Silicon Nitride Stack Gate Dielectric

2011 ◽  
Vol 110-116 ◽  
pp. 5442-5446
Author(s):  
Li Jun Xu ◽  
He Ming Zhang ◽  
Hui Yong Hu ◽  
Xiao Bo Xu ◽  
Jian Li Ma
Keyword(s):  
Dielectric Constant ◽  
Silicon Nitride ◽  
Gate Dielectric ◽  
Device Simulation ◽  
Tunneling Current ◽  
Simulation Software ◽  
Direct Tunneling ◽  
Direct Tunneling Current ◽  
Application Limit ◽  
Mos Device

As the size of MOS device scaled down to sub 100nm, the direct tunneling current of gate oxide increases more and more. Using silicon nitride as gate dielectric can solve this problem effectively in some time due to the dielectric constant of silicon nitride is larger than silica’s.This paper derived the dielectric constant of silicon nitride stack gate dielectric,and simulated the direct tunneling current of strained MOS device with silica and silicon nitride gate dielectric through device simulation software ISE TCAD10.0,studied the direct tunneling current of strained MOS device with silicon nitride stack gate dielectric change with the variation of some parameters and the application limit of silicon nitride material.

Low Leakage Current Patterned Polymeric Transistors with PAG Assisted Cross-linking PVP as Gate Dielectric and Passivation Layers

2008 ◽  
Vol 1091 ◽  
Author(s):  
Cheng-Chin Liu ◽  
Kuo-Jui Chang ◽  
Feng-Yu Yang ◽  
Ta-Chuan Liao ◽  
Huang-Chung Cheng
Keyword(s):  
Low Temperature ◽  
Leakage Current ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Thin Film Transistor ◽  
Subthreshold Swing ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Passivation Layers ◽  
Amorphous Si

AbstractWe have successfully proposed a patterned P3HT thin-film transistor with cross-linked PVP as a passivation material which was cured at low temperature. The active P3HT layer was isolated via photolithographic technique and O2 plasma RIE etching process. In this method, the leakage current could be reduced effectively compared with that of non-patterned device. Although the mobility was degraded 40 %, but the on/off ratio was significantly improved by over three orders and also the subthreshold swing was compatible with the amorphous Si-TFTs (∼1.5 V/decade). Moreover, we also employed this low temperature curing PVP (120 0C) films as the gate dielectrics which exhibited excellent insulating property with high on/off ratio 1.58×104 and good subthreshold swing 1.66 V/decade.

Modeling of direct tunneling current through gate dielectric stacks

2000 ◽  
Vol 47 (10) ◽  
pp. 1851-1857 ◽  
Author(s):  
S. Mudanai ◽  
Yang-Yu Fan ◽  
Qiqing Ouyang ◽  
A.F. Tasch ◽  
S.K. Banerjee
Keyword(s):  
Gate Dielectric ◽  
Tunneling Current ◽  
Direct Tunneling ◽  
Direct Tunneling Current
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