scholarly journals Q-Factor Performance of 28 nm-Node High-K Gate Dielectric under DPN Treatment at Different Annealing Temperatures

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2086
Author(s):  
Chii-Wen Chen ◽  
Shea-Jue Wang ◽  
Wen-Ching Hsieh ◽  
Jian-Ming Chen ◽  
Te Jong ◽  
...  
Keyword(s):  
Figure Of Merit ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Nitrogen Concentration ◽  
Point Of View ◽  
Tunneling Effect ◽  
Q Factor ◽  
High K ◽  
Different Temperatures

Q-factor is a reasonable index to investigate the integrity of circuits or devices in terms of their energy or charge storage capabilities. We use this figure of merit to explore the deposition quality of nano-node high-k gate dielectrics by decoupled-plasma nitridation at different temperatures with a fixed nitrogen concentration. This is very important in radio-frequency applications. From the point of view of the Q-factor, the device treated at a higher annealing temperature clearly demonstrates a better Q-factor value. Another interesting observation is the appearance of two troughs in the Q-VGS characteristics, which are strongly related to either the series parasitic capacitance, the tunneling effect, or both.

Hrtem Investigation of Effect of Various Rare Earth Oxide Dopants on Epitaxial Zirconia High-k Gate Dielectrics

2002 ◽  
Vol 747 ◽  
Author(s):  
Takanori Kiguchi ◽  
Naoki Wakiya ◽  
Kazuo Shinozaki ◽  
Nobuyasu Mzutani
Keyword(s):  
Rare Earth ◽  
Ionic Radius ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Rare Earth Oxide ◽  
The Other ◽  
High K ◽  
Capacitance Voltage

ABSTRACTThe effects of several rare earth oxide on the capacitance-voltage (C-V) characteristics and the SiO2 interlayer growth of ZrO2 based gate dielectrics were examined. The width of the hysteresis window of La2O3 stabilized ZrO2 (LaSZ) gate dielectric was only 0.2V, on the other hands, that of Sc2O3 stabilized ZrO2 (ScSZ) gate dielectric was 1.4V HRTEM analysis indicated that the growth of SiO2 interlayer of RSZ (R=Sm,Nd,La) gate dielectric was about 1nm, which was less than half of the ScSZ one. These results indicate the advantage of the ZrO2 gate dielectric doped with rare earth oxide composed of larger ionic radius cation.

Hrtem Investigation of Effect of Various Rare Earth Oxide Dopants on Epitaxial Zirconia High-K Gate Dielectrics

2002 ◽  
Vol 745 ◽  
Author(s):  
Takanori Kiguchi ◽  
Naoki Wakiya ◽  
Kazuo Shinozaki ◽  
Nobuyasu Mzutani
Keyword(s):  
Rare Earth ◽  
Ionic Radius ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Rare Earth Oxide ◽  
The Other ◽  
High K ◽  
Capacitance Voltage

ABSTRACTThe effects of several rare earth oxide on the capacitance-voltage (C-V) characteristics and the SiO2 interlayer growth of ZrO2 based gate dielectrics were examined. The width of the hysteresis window of La2O3 stabilized ZrO2 (LaSZ) gate dielectric was only 0.2V, on the other hands, that of Sc2O3 stabilized ZrO2 (ScSZ) gate dielectric was 1.4V HRTEM analysis indicated that the growth of SiO2 interlayer of RSZ (R=Sm,Nd,La) gate dielectric was about 1nm, which was less than half of the ScSZ one. These results indicate the advantage of the ZrO2 gate dielectric doped with rare earth oxide composed of larger ionic radius cation.

Characterization of LaxHfyO Gate Dielectrics in 4H-SiC MOS Capacitor

2014 ◽  
Vol 778-780 ◽  
pp. 549-552 ◽  
Author(s):  
Jing Hua Xia ◽  
David M. Martin ◽  
Sethu Saveda Suvanam ◽  
Carl Mikael Zetterling ◽  
Mikael Östling
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Atomic Layer ◽  
Deposition Process ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
Layer Deposition ◽  
High K ◽  
Film Characteristics

LaxHfyO nanolaminated thin film deposited using atomic layer deposition process has been studied as a high-K gate dielectric in 4H-SiC MOS capacitors. The electrical and nano-laminated film characteristics were studied with increasing post deposition annealing (PDA) in N2O ambient. The result shows that high quality LaxHfyO nano-laminated thin films with good interface and bulk qualities are fabricated using high PDA temperature.

Methods to Improve Properties of Gate Dielectrics in Metal-Oxide-Semiconductor

2012 ◽  
Vol 463-464 ◽  
pp. 1341-1345 ◽  
Author(s):  
Chong Liu ◽  
Xiao Li Fan
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Dielectric Materials ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Physical Limitation ◽  
Low Leakage ◽  
Mos Devices ◽  
Low Leakage Current ◽  
High K

This essay aims to introduce development of gate dielectrics. In present-day society, Si-based MOS has met its physical limitation. Scientists are trying to find a better material to reduce the thickness and dimension of MOS devices. While substrate materials are required to have a higher mobility, gate dielectrics are expected to have high k, low Dit and low leakage current. I conclude dielectrics in both Si-based and Ge-based MOS devices and several measures to improve the properties of these gate dielectric materials. I also introduce studies on process in our group and some achievements we have got. Significantly, this essay points out the special interest in rare-earth oxides functioning as gate dielectrics in recent years and summarizes the advantages and problems should be resolved in future.

Q-factor Integrity of 28nm-node High-k Gate Dielectric

2020 ◽  
Author(s):  
Ying-Jun Deng ◽  
Hao-Lun Hu ◽  
Yu-Han Liang ◽  
Jian-Ming Chen ◽  
Ching-Chuan Chou ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Q Factor ◽  
High K ◽  
High K Gate Dielectric

Effective Dielectric Thickness Scaling for High-K Gate Dielectric Mosfets

2002 ◽  
Vol 716 ◽  
Author(s):  
Krishna Kumar Bhuwalka ◽  
Nihar R. Mohapatra ◽  
Siva G. Narendra ◽  
V Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Channel Length ◽  
Short Channel ◽  
Dielectric Thickness ◽  
High K ◽  
Fringing Field ◽  
High K Dielectric ◽  
Physical Thickness

AbstractIt has been shown recently that the short channel performance worsens for high-K dielectric MOSFETs as the physical thickness to the channel length ratio increases, even when the effective oxide thickness (EOT) is kept identical to that of SiO2. In this work we have systematically evaluated the effective dielectric thickness for different Kgate to achieve targeted threshold voltage (Vt), drain-induced barrier lowering (DIBL) and Ion/Ioff ratio for different technology generations down to 50 nm using 2-Dimensional process and device simulations. Our results clearly show that the oxide thickness scaling for high-K gate dielectrics and SiO2 follow different trends and the fringing field effects must be taken into account for estimation of effective dielectric thickness when SiO2 is replaced by a high-K dielectric.

Novel Dielectric Materials for Future Transistor Generations

2006 ◽  
Vol 16 (01) ◽  
pp. 221-239 ◽  
Author(s):  
GENNADI BERSUKER ◽  
BYOUNG HUN LEE ◽  
HOWARD R. HUFF
Keyword(s):  
Gate Dielectric ◽  
Dielectric Materials ◽  
Structural Defects ◽  
Electrical Characteristics ◽  
Si Substrate ◽  
Voltage Instability ◽  
Fixed Charges ◽  
High K ◽  
High K Materials

Relations between the electronic properties of high-k materials and electrical characteristics of high-k transistor are discussed. It is pointed out that the intrinsic limitations of these materials from the standpoint of gate dielectric applications are related to the presence of d-electrons, which facilitate high values of the dielectric constant. It is shown that the presence of structural defects responsible for electron trapping and fixed charges, and the dielectrics' tendency for crystallization and phase separation induce threshold voltage instability and mobility degradation in high-k transistors. The quality of the SiO 2-like layer at the high-k/ Si substrate interface, as well as dielectric interaction with the gate electrode, may significantly affect device characteristics.

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