Reliability and Copper Interconnections with Low Dielectric Constant Materials

1998 ◽  
Vol 511 ◽  
Author(s):  
C-K. Hu

ABSTRACTThe materials, process integration, and reliability issues in the development of multilevel electroplated Cu/polyimide on-chip interconnections are described. A combination of: good diffusion/adhesion barrier layers consisting of a metal liner plus the insulator Si3N4, and W stud/Si contacts resulted in a highly reliable IC chip. Electromigration of Cu damascene lines in both SiO2 and polyimide structures was investigated. Similar void growth was observed at the cathode ends of both the interconnect systems. However, the shapes of protrusions at the anode ends of the lines were different. Although the activation energies for both near bamboo-like Cu/SiO2 and Cu/polyimide were both 1.1 eV, the electromigration lifetime of the former was significantly longer. The difference is largely attributable to the poorer thermal conductivity of polyimide.

1996 ◽  
Vol 443 ◽  
Author(s):  
Neil H. Hendricks

AbstractFor over two years, intensive efforts at SEMATECH and elsewhere have focused on identifying low dielectric constant (low ε) materials which possess all of the required properties and processing characteristics needed for integration into standard IC fabrication lines. To date, no material candidate has been shown to satisfy this impressive list of requirements. For some candidates, drawbacks related to material properties such as poor thermal stability or electrical performance have been identified; in other cases, problems in process integration, for example difficulties in patterning have stalled progress.In this paper, most of the current leading candidates for the low ε IC IMC application are identified and discussed. An attempt is made to correlate structure/property relationships in these materials with their relative attributes and deficiencies as they relate to the IMD application. Key differences in chemistry and property/processing characteristics are contrasted for low c silicon-oxygen polymers and for purely organic polymers. Novel dielectrics such as porous organic and inorganic thin films are also discussed in terms of their properties and associated process integration challenges. Since the needs for global planarization and low c IMD are occurring within roughly the same generation of minimum feature size (˜ 0.25 μm), the chemical mechanical polishing (CMP) of low dielectric constant thin films and/or of SiO2 layers deposited above them is briefly discussed. Both subtractive metalization and damascene processes are included, and the required low dielectric constant film properties and processing characteristics are contrasted for each process. Finally, the author's views on future trends in low dielectric constant materials development are presented, with an emphasis on identifying the types of chemical structures which may prove viable for this most demanding of all polymer film applications.


1999 ◽  
Vol 565 ◽  
Author(s):  
Bin Zhao ◽  
Maureen Brongo

AbstractAdvanced on-chip interconnects using new materials and new integration architectures are necessary for current and future IC chips in order to meet the requirements in performance, reliability and manufacturing cost. Insulating materials with low dielectric constant (low-κ) and conductive materials with low-resistivity have drawn significant attention for their possible applications in IC interconnects. Dual damascene interconnect integration architectures not only offer process simplification and low cost, but also enable the use of low-resistive Cu for interconnect wiring. Use of low-κ materials in dual damascene architecture is challenging due to material and processing issues. In this paper, the evolution of advanced interconnects, materials and technology options, and some recent achievements in advanced interconnect systems of low-κ dielectric and dual damascene architectures for both Al and Cu metallization are reviewed and discussed.


1996 ◽  
Vol 427 ◽  
Author(s):  
Bin Zhao ◽  
Shi-Qing Wang ◽  
Steven Anderson ◽  
Robbie Lam ◽  
Marcy Fiebig ◽  
...  

AbstractIn high performance integrated circuits, low dielectric constant (low-ε) materials are required as inter-level dielectric (ILD) for on-chip interconnect to provide advantages in high speed, low dynamic power dissipation and low cross-talk noise. A variety of low dielectric constant materials, which include fluorinated silicon-oxide, porous silica and porous organic materials, chemical vapor deposited and spin-on deposited (SOD) organic materials, have been developed or are under development to fulfill this need. In this paper, we first review the need and integration architecture of low-ε materials for on-chip interconnect. Then, we discuss the consequence of using low-ε materials as ILD in advanced interconnect with emphasis on the ILD electrical characteristics and the interconnect reliability. Although the focus is on several new promising SOD low-ε materials, the developed evaluation methodology is applicable to other type low-ε materials as well.


1999 ◽  
Vol 564 ◽  
Author(s):  
Bin Zhao ◽  
Maureen Brongo

AbstractAdvanced on-chip interconnects using new materials and new integration architectures are necessary for current and future IC chips in order to meet the requirements in performance, reliability and manufacturing cost. Insulating materials with low dielectric constant (low-κ) and conductive materials with low-resistivity have drawn significant attention for their possible applications in IC interconnects. Dual damascene interconnect integration architectures not only offer process simplification and low cost, but also enable the use of low-resistive Cu for interconnect wiring. Use of low-κ materials in dual damascene architecture is challenging due to material and processing issues. In this paper, the evolution of advanced interconnects, materials and technology options, and some recent achievements in advanced interconnect systems of low-κ dielectric and dual damascene architectures for both Al and Cu metallization are reviewed and discussed.


1999 ◽  
Vol 565 ◽  
Author(s):  
Hideki Gomi ◽  
Koji Kishimoto ◽  
Tatsuya Usami ◽  
Ken-ichi Koyanagi ◽  
Takashi Yokoyama ◽  
...  

AbstractThe technologies utilizing Fluorinated Silicon Oxide (FSG, k=3.6) and Hydrogen Silsesquioxane (HSQ, k=3.0) have been established for 0.25-μm and 0.18-μm generation ULSIs. However, low-k materials for the next generation ULSIs, which have a dielectric constant of less than 3.0, have not become mature yet. In this paper, we review process integration issues in applying FSG and HSQ, and describe integration results and device performance using Fluorinated Amorphous Carbon (a-C:F, k=2.5) as one of the promising low-k materials for the next generation ULSIs.


1999 ◽  
Vol 564 ◽  
Author(s):  
Hideki Gomi ◽  
Koji Kishimoto ◽  
Tatsuya Usami ◽  
Ken-ichi Koyanagi ◽  
Takashi Yokoyama ◽  
...  

AbstractThe technologies utilizing Fluorinated Silicon Oxide (FSG, k=3.6) and Hydrogen Silsesquioxane (HSQ, k=3.0) have been established for 0.25-µm and 0.1 8-µm generation ULSIs. However, low-k materials for the next generation ULSIs, which have a dielectric constant of less than 3.0, have not become mature yet. In this paper, we review process integration issues in applying FSG and HSQ, and describe integration results and device performance using Fluorinated Amorphous Carbon (a-C:F, k=2.5) as one of the promising low-k materials for the next generation ULSIs.


2004 ◽  
Vol 151 (6) ◽  
pp. F146 ◽  
Author(s):  
Shou-Yi Chang ◽  
Tzu-Jen Chou ◽  
Yung-Cheng Lu ◽  
Syun-Ming Jang ◽  
Su-Jien Lin ◽  
...  

Sign in / Sign up

Export Citation Format

Share Document