Reaction Processes for Low Temperature (<150°C) Plasma Enhanced Deposition of Hydrogenated Amorphous Silicon Thin-Film Transistors on Transparent Plastic Substrates

1998 ◽  
Vol 508 ◽  
Author(s):  
Gregory N. Parsons ◽  
Chien-Sheng Yang ◽  
Tonya M. Klein ◽  
Laura Smith
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Low Temperature ◽  
Amorphous Silicon ◽  
Charge Trapping ◽  
Rf Plasma ◽  
Processing Temperature ◽  
Silicon Thin Film ◽  
Transparent Plastic ◽  
Plastic Substrates

AbstractThis article presents mechanisms for low temperature (<150°C) rf plasma enhanced chemical vapor deposition of silicon and silicon nitride thin films that lead to sufficient electronic quality for thin film transistor (TFT) fabrication and operation. For silicon deposition, hydrogen abstraction and etching, and silicon disproportionation reactions are identified that can lead to optimized hydrogen concentration and bonding environments at <150°C. Nitrogen dilution of SiH4/NH3 mixtures during silicon nitride deposition at low temperatures helps promote N-H bonding, leading to reduced charge trapping. Good quality amorphous silicon TFT's fabricated with a maximum processing temperature of 110 °C are demonstrated on flexible transparent plastic substrates. Transistors formed with the same process on glass and plastic show linear mobilities of 0.33 and 0.12 cm2/Vs, respectively, with ION/IOFF ratios > 106.

Reaction Processes for Low Temperature (<150°C) Plasma Enhanced Deposition of Hydrogenated Amorphous Silicon Thin Film Transistors on Transparent Plastic Substrates

1998 ◽  
Vol 507 ◽  
Author(s):  
Gregory N. Parsons ◽  
Chien-Sheng Yang ◽  
Tonya M. Klein ◽  
Laura Smith
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Low Temperature ◽  
Amorphous Silicon ◽  
Charge Trapping ◽  
Rf Plasma ◽  
Processing Temperature ◽  
Silicon Thin Film ◽  
Transparent Plastic ◽  
Plastic Substrates

ABSTRACTThis article presents mechanisms for low temperature (<150°C) rf plasma enhanced chemical vapor deposition of silicon and silicon nitride thin films that lead to sufficient electronic quality for thin film transistor (TFT) fabrication and operation. For silicon deposition, hydrogen abstraction and etching, and silicon disproportionation reactions are identified that can lead to optimized hydrogen concentration and bonding environments at <150°C. Nitrogen dilution of SiH4/NH3 mixtures during silicon nitride deposition at low temperatures helps promote N-H bonding, leading to reduced charge trapping. Good quality amorphous silicon TFT's fabricated with a maximum processing temperature of 110°C are demonstrated on flexible transparent plastic substrates. Transistors formed with the same process on glass and plastic show linear mobilities of 0.33 and 0.12 cm2/Vs, respectively, with ION/IOFF ratios > 106.

Low Temperature Thin-Film Microelectromechanical Devices on Plastic Substrates

2000 ◽  
Vol 609 ◽  
Author(s):  
M. Boucinha ◽  
P. Brogueira ◽  
V. Chu ◽  
P. Alpuim ◽  
J. P. Conde
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Amorphous Silicon ◽  
Critical Voltage ◽  
Processing Temperature ◽  
Free Standing ◽  
Plastic Substrates ◽  
Microelectromechanical Devices ◽  
Bridge Structures ◽  
Mechanical Actuation

ABSTRACTAir-gap micromachined structures such as bridges and cantilevers were fabricated on 50 and 125 µm-thick polyethylene terephthalate (PET) plastic substrates. The maximum processing temperature using PET is limited to 110 °C. Two surface micromachining processes on PET which used two different sacrificial layers - photoresist and Al - were developed. Several materials were used as structural layers in the microstructures including Al, TiW, amorphous silicon (a-Si:H) and a bilayer of a-Si:H and Al. The maximum length of free-standing bridges and cantilevers is discussed as a function of the fabrication process. The bridge structures were actuated electrostatically, in a DC switch setup configuration, and the critical voltage as a function of the length was measured. Mechanical actuation and optical detection were used, in an AC mode, for the measurement of the resonance frequency of bridge structures.

Low temperature polycrystalline silicon thin film transistor with silicon nitride ion stopper

1996 ◽  
Vol 17 (6) ◽  
pp. 258-260 ◽  
Author(s):  
Kyung Ha Lee ◽  
Young Min Jhon ◽  
Hyuk Jin Cha ◽  
Jin Jang
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Low Temperature ◽  
Polycrystalline Silicon ◽  
Thin Film Transistor ◽  
Silicon Thin Film

Self-aligned Amorphous Silicon Thin Film Transistors with Mobility above 1 cm2V−1s−1fabricated at 300°C on Clear Plastic Substrates

2008 ◽  
Vol 1066 ◽  
Author(s):  
Kunigunde H Cherenack ◽  
Alex Z Kattamis ◽  
Bahman Hekmatshoar ◽  
James C Sturm ◽  
Sigurd Wagner
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Fabrication Process ◽  
Plastic Substrate ◽  
Silicon Thin Film ◽  
Free Standing ◽  
Plastic Substrates ◽  
Effective Mobility ◽  
Clear Plastic

ABSTRACTWe have developed a fabrication process for amorphous-silicon thin-film transistors (a-Si:H TFTs) on free-standing clear plastic substrates at temperatures up to 300°C. The 300°C fabrication process is made possible by using a unique clear plastic substrate that has a very low coefficient of thermal expansion (CTE < 10ppm/°C) and a glass transition temperature higher than 300°C. Our TFTs have a conventional inverted-staggered gate back-channel passivated geometry, which we designed to achieve two goals: accurate overlay alignment and a high effective mobility. A requirement that becomes particularly difficult to meet in the making of TFT backplanes on plastic foil at 300°C is minimizing overlay misalignment. Even though we use a substrate that has a relatively low CTE, accurately aligning the TFTs on the free-standing, 70-micrometer thick substrate is challenging. To deal with this immediate challenge, and to continue developing processes for free-standing web substrates, we are introducing techniques for self-alignment to our TFT fabrication process. We have self-aligned the channel to the gate by exposing through the clear plastic substrate. To raise the effective mobility of our TFTs we reduced the series resistance by decreasing the thickness of the amorphous silicon layer between the source-drain contacts and the accumulation layer in the channel. The back-channel passivated structure allows us to decrease the thickness of the a-Si:H active layer down to around 20nm. These changes have enabled us to raise the effective field effect mobility on clear plastic to values above 1 cm2V−1s−1

Charge trapping effects in amorphous silicon/silicon nitride thin film transistors

1987 ◽  
Vol 97-98 ◽  
pp. 903-906 ◽  
Author(s):  
A.R. Hepburn ◽  
C. Main ◽  
J.M. Marshall ◽  
C. van Berkel ◽  
M.J. Powell
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Charge Trapping ◽  
Silicon Silicon ◽  
Trapping Effects

Threshold Voltage Shifts in Amorphous Silicon Thin Film Transistors under Bias Stress

1990 ◽  
Vol 192 ◽  
Author(s):  
Tetsu Ogawa ◽  
Sadayoshi Hotta ◽  
Horoyoshi Takezawa
Keyword(s):  
Thin Film ◽  
Temperature Dependence ◽  
Amorphous Silicon ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Charge Trapping ◽  
The Other ◽  
Time Dependent ◽  
Silicon Thin Film ◽  
Bias Stress

ABSTRACTThrough the time and temperature dependence measurements on threshold voltage shifts (Δ VT) in amorphous silicon thin film transistors, it has been found that two separate instability mechanisms exist; within short stress time ranges Δ Vτ increases as log t and this behavior corresponds to charge trapping in SiN. On the other hand, in long stress time ranges Δ VT increases as t t/4 and can be explained by time-dependent creation of trap in a-Si.

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