Stability of low-temperature amorphous silicon thin film transistors formed on glass and transparent plastic substrates

2000 ◽  
Vol 18 (2) ◽  
pp. 683 ◽  
Author(s):  
C.-S. Yang ◽  
L. L. Smith ◽  
C. B. Arthur ◽  
G. N. Parsons
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Silicon Thin Film ◽  
Transparent Plastic ◽  
Plastic Substrates

Reaction Processes for Low Temperature (<150°C) Plasma Enhanced Deposition of Hydrogenated Amorphous Silicon Thin-Film Transistors on Transparent Plastic Substrates

1998 ◽  
Vol 508 ◽  
Author(s):  
Gregory N. Parsons ◽  
Chien-Sheng Yang ◽  
Tonya M. Klein ◽  
Laura Smith
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Low Temperature ◽  
Amorphous Silicon ◽  
Charge Trapping ◽  
Rf Plasma ◽  
Processing Temperature ◽  
Silicon Thin Film ◽  
Transparent Plastic ◽  
Plastic Substrates

AbstractThis article presents mechanisms for low temperature (<150°C) rf plasma enhanced chemical vapor deposition of silicon and silicon nitride thin films that lead to sufficient electronic quality for thin film transistor (TFT) fabrication and operation. For silicon deposition, hydrogen abstraction and etching, and silicon disproportionation reactions are identified that can lead to optimized hydrogen concentration and bonding environments at <150°C. Nitrogen dilution of SiH4/NH3 mixtures during silicon nitride deposition at low temperatures helps promote N-H bonding, leading to reduced charge trapping. Good quality amorphous silicon TFT's fabricated with a maximum processing temperature of 110 °C are demonstrated on flexible transparent plastic substrates. Transistors formed with the same process on glass and plastic show linear mobilities of 0.33 and 0.12 cm2/Vs, respectively, with ION/IOFF ratios > 106.

Reaction Processes for Low Temperature (<150°C) Plasma Enhanced Deposition of Hydrogenated Amorphous Silicon Thin Film Transistors on Transparent Plastic Substrates

1998 ◽  
Vol 507 ◽  
Author(s):  
Gregory N. Parsons ◽  
Chien-Sheng Yang ◽  
Tonya M. Klein ◽  
Laura Smith
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Low Temperature ◽  
Amorphous Silicon ◽  
Charge Trapping ◽  
Rf Plasma ◽  
Processing Temperature ◽  
Silicon Thin Film ◽  
Transparent Plastic ◽  
Plastic Substrates

ABSTRACTThis article presents mechanisms for low temperature (<150°C) rf plasma enhanced chemical vapor deposition of silicon and silicon nitride thin films that lead to sufficient electronic quality for thin film transistor (TFT) fabrication and operation. For silicon deposition, hydrogen abstraction and etching, and silicon disproportionation reactions are identified that can lead to optimized hydrogen concentration and bonding environments at <150°C. Nitrogen dilution of SiH4/NH3 mixtures during silicon nitride deposition at low temperatures helps promote N-H bonding, leading to reduced charge trapping. Good quality amorphous silicon TFT's fabricated with a maximum processing temperature of 110°C are demonstrated on flexible transparent plastic substrates. Transistors formed with the same process on glass and plastic show linear mobilities of 0.33 and 0.12 cm2/Vs, respectively, with ION/IOFF ratios > 106.

Self-aligned Amorphous Silicon Thin Film Transistors with Mobility above 1 cm2V−1s−1fabricated at 300°C on Clear Plastic Substrates

2008 ◽  
Vol 1066 ◽  
Author(s):  
Kunigunde H Cherenack ◽  
Alex Z Kattamis ◽  
Bahman Hekmatshoar ◽  
James C Sturm ◽  
Sigurd Wagner
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Fabrication Process ◽  
Plastic Substrate ◽  
Silicon Thin Film ◽  
Free Standing ◽  
Plastic Substrates ◽  
Effective Mobility ◽  
Clear Plastic

ABSTRACTWe have developed a fabrication process for amorphous-silicon thin-film transistors (a-Si:H TFTs) on free-standing clear plastic substrates at temperatures up to 300°C. The 300°C fabrication process is made possible by using a unique clear plastic substrate that has a very low coefficient of thermal expansion (CTE < 10ppm/°C) and a glass transition temperature higher than 300°C. Our TFTs have a conventional inverted-staggered gate back-channel passivated geometry, which we designed to achieve two goals: accurate overlay alignment and a high effective mobility. A requirement that becomes particularly difficult to meet in the making of TFT backplanes on plastic foil at 300°C is minimizing overlay misalignment. Even though we use a substrate that has a relatively low CTE, accurately aligning the TFTs on the free-standing, 70-micrometer thick substrate is challenging. To deal with this immediate challenge, and to continue developing processes for free-standing web substrates, we are introducing techniques for self-alignment to our TFT fabrication process. We have self-aligned the channel to the gate by exposing through the clear plastic substrate. To raise the effective mobility of our TFTs we reduced the series resistance by decreasing the thickness of the amorphous silicon layer between the source-drain contacts and the accumulation layer in the channel. The back-channel passivated structure allows us to decrease the thickness of the a-Si:H active layer down to around 20nm. These changes have enabled us to raise the effective field effect mobility on clear plastic to values above 1 cm2V−1s−1

scholarly journals Low-Temperature Passivation of Amorphous-Silicon Thin-Film Transistors With Supercritical Fluids

2007 ◽  
Vol 28 (7) ◽  
pp. 584-586 ◽  
Author(s):  
Chih-Tsung Tsai ◽  
Po-Tsun Liu ◽  
Ting-Chang Chang ◽  
Chen-Wen Wang ◽  
Po-Yu Yang ◽  
...  
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Amorphous Silicon ◽  
Supercritical Fluids ◽  
Thin Film Transistors ◽  
Silicon Thin Film
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